78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
/*
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* tc358767_dsi2edp.h: dsi-edp controller tc358767 driver headers.
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*
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* Copyright (c) 2012-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __DRIVERS_VIDEO_TEGRA_DC_TC358767_DSI2EDP_H
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#define __DRIVERS_VIDEO_TEGRA_DC_TC358767_DSI2EDP_H
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struct tegra_dsi2edp {
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struct tegra_dc_dsi_data *dsi;
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struct i2c_client *client_i2c;
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struct regmap *regmap;
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struct tegra_dc_mode *mode;
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bool enabled;
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bool i2c_shutdown;
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struct mutex lock;
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};
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#define DP0_SRC_CTRL 0x06a0
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#define DP1_SRC_CTRL 0x07a0
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#define SYS_PLL_PARAM 0x0918
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#define DP_PHY_CTRL 0x0800
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#define DP1_PLL_CTRL 0x0904
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#define DP0_PLL_CTRL 0x0900
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#define PXL_PLL_PARAM 0x0914
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#define PXL_PLL_CTRL 0x0908
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#define DP0_AUX_ADDR 0x0668
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#define DP0_AUX_CFG1 0x0664
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#define DP0_AUX_CFG0 0x0660
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#define DP0_AUX_WDATA0 0x066c
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#define DP0_SNK_LTCTRL 0x06e4
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#define DP0_LTLOOP_CTRL 0x06d8
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#define DP0_CTRL 0x0600
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#define PPI_TX_RX_TA 0x013c
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#define PPI_LPTX_TIME_CNT 0x0114
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#define PPI_D0S_CLRSIPOCOUNT 0x0164
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#define PPI_D1S_CLRSIPOCOUNT 0x0168
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#define PPI_D2S_CLRSIPOCOUNT 0x016c
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#define PPI_D3S_CLRSIPOCOUNT 0x0170
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#define PPI_LANE_ENABLE 0x0134
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#define DSI_LANE_ENABLE 0x0210
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#define PPI_STARTPPI 0x0104
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#define DSI_STARTDSI 0x0204
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#define VIDEO_PATH0_CTRL 0x0450
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#define H_TIMING_CTRL01 0x0454
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#define H_TIMING_CTRL02 0x0458
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#define V_TIMING_CTRL01 0x045c
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#define V_TIMING_CTRL02 0x0460
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#define VIDEO_FRAME_TIMING_UPLOAD_ENB0 0x0464
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#define DP0_VIDEO_SYNC_DELAY 0x0644
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#define DP0_TOT_VAL 0x0648
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#define DP0_START_VAL 0x064c
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#define DP0_ACTIVE_VAL 0x0650
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#define DP0_SYNC_VAL 0x0654
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#define DP0_MISC 0x0658
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#define DP0_AUX_ADDR 0x0668
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#define VIDEO_MN_GEN0 0x0610
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#define VIDEO_MN_GEN1 0x0614
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#define SYS_CTRL 0x0510
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#endif
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