1208 lines
30 KiB
C
1208 lines
30 KiB
C
/*
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* dc.h: Headers required for tegra dc and dependent modules.
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Erik Gilling <konkers@google.com>
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*
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* Copyright (c) 2010-2019, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_DC_H
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#define __MACH_TEGRA_DC_H
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#include <linux/pm.h>
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#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/fb.h>
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#include <linux/platform/tegra/emc_bwmgr.h>
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#include <linux/platform/tegra/isomgr.h>
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#include <drm/drm_fixed.h>
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#include <linux/nvhost.h>
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#include <linux/extcon.h>
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#include <video/tegra_dc_ext_kernel.h>
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#include <uapi/video/tegra_dc_ext.h>
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#include "dc_extras.h"
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#define DEFAULT_FPGA_FREQ_KHZ 160000
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#define TEGRA_DC_EXT_FLIP_MAX_WINDOW 6
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extern struct fb_videomode tegra_dc_vga_mode;
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enum {
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TEGRA_HPD_STATE_FORCE_DEASSERT = -1,
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TEGRA_HPD_STATE_NORMAL = 0,
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TEGRA_HPD_STATE_FORCE_ASSERT = 1,
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};
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/* DSI pixel data format */
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enum {
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TEGRA_DSI_PIXEL_FORMAT_16BIT_P,
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TEGRA_DSI_PIXEL_FORMAT_18BIT_P,
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TEGRA_DSI_PIXEL_FORMAT_18BIT_NP,
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TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
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TEGRA_DSI_PIXEL_FORMAT_8BIT_DSC,
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TEGRA_DSI_PIXEL_FORMAT_12BIT_DSC,
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TEGRA_DSI_PIXEL_FORMAT_16BIT_DSC,
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};
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/* DSI virtual channel number */
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enum {
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TEGRA_DSI_VIRTUAL_CHANNEL_0,
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TEGRA_DSI_VIRTUAL_CHANNEL_1,
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TEGRA_DSI_VIRTUAL_CHANNEL_2,
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TEGRA_DSI_VIRTUAL_CHANNEL_3,
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};
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/* DSI transmit method for video data */
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enum {
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TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE,
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TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
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};
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/* DSI HS clock mode */
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enum {
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TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
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TEGRA_DSI_VIDEO_CLOCK_TX_ONLY,
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};
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/* DSI burst mode setting in video mode. Each mode is assigned with a
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* fixed value. The rationale behind this is to avoid change of these
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* values, since the calculation of dsi clock depends on them. */
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enum {
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TEGRA_DSI_VIDEO_NONE_BURST_MODE = 0,
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TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END = 1,
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TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
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TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
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TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
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TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
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TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
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};
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enum {
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TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT = 1,
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TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD = 2,
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TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP = 3,
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};
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/* Split Link Type */
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enum {
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TEGRA_DSI_SPLIT_LINK_A_B = 1,
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TEGRA_DSI_SPLIT_LINK_C_D = 2,
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TEGRA_DSI_SPLIT_LINK_A_B_C_D = 3,
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};
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enum {
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TEGRA_DSI_PACKET_CMD,
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TEGRA_DSI_DELAY_MS,
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TEGRA_DSI_GPIO_SET,
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TEGRA_DSI_SEND_FRAME,
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TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD,
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TEGRA_DSI_DELAY_US,
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};
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enum {
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TEGRA_DSI_LINK0,
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TEGRA_DSI_LINK1,
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};
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#define TEGRA_DC_TOPOLOGY_INVALID -2
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#define TEGRA_DC_TOPOLOGY_NARGS 3
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#define TEGRA_DC_TOPOLOGY_RESTORE -1
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#define TEGRA_DC_TOPOLOGY_ARG_MIN -1
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#define TEGRA_DC_TOPOLOGY_ARG_MAX 10
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struct tegra_dsi_cmd {
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u8 cmd_type;
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u8 data_id;
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union {
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u16 data_len;
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u16 delay_ms;
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u16 delay_us;
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unsigned gpio;
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u16 frame_cnt;
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struct {
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u8 data0;
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u8 data1;
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} sp;
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} sp_len_dly;
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u8 *pdata;
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u8 link_id;
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bool club_cmd;
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};
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#define CMD_CLUBBED true
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#define CMD_NOT_CLUBBED false
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#define DSI_GENERIC_LONG_WRITE 0x29
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#define DSI_DCS_LONG_WRITE 0x39
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#define DSI_GENERIC_SHORT_WRITE_1_PARAMS 0x13
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#define DSI_GENERIC_SHORT_WRITE_2_PARAMS 0x23
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#define DSI_DCS_WRITE_0_PARAM 0x05
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#define DSI_DCS_WRITE_1_PARAM 0x15
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#define DSI_DCS_SET_ADDR_MODE 0x36
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#define DSI_DCS_EXIT_SLEEP_MODE 0x11
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#define DSI_DCS_ENTER_SLEEP_MODE 0x10
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#define DSI_DCS_SET_DISPLAY_ON 0x29
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#define DSI_DCS_SET_DISPLAY_OFF 0x28
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#define DSI_DCS_SET_TEARING_EFFECT_OFF 0x34
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#define DSI_DCS_SET_TEARING_EFFECT_ON 0x35
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#define DSI_DCS_NO_OP 0x0
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#define DSI_NULL_PKT_NO_DATA 0x9
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#define DSI_BLANKING_PKT_NO_DATA 0x19
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#define IS_DSI_SHORT_PKT(cmd) ((cmd.data_id == DSI_DCS_WRITE_0_PARAM) ||\
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(cmd.data_id == DSI_DCS_WRITE_1_PARAM) ||\
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(cmd.data_id == DSI_GENERIC_SHORT_WRITE_1_PARAMS) ||\
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(cmd.data_id == DSI_GENERIC_SHORT_WRITE_2_PARAMS))
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#define _DSI_CMD_SHORT(di, p0, p1, lnk_id, _cmd_type, club) { \
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.cmd_type = _cmd_type, \
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.data_id = di, \
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.sp_len_dly.sp.data0 = p0, \
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.sp_len_dly.sp.data1 = p1, \
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.link_id = lnk_id, \
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.club_cmd = club,\
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}
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#define DSI_CMD_VBLANK_SHORT(di, p0, p1, club) \
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_DSI_CMD_SHORT(di, p0, p1, TEGRA_DSI_LINK0,\
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TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD, club)
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#define DSI_CMD_SHORT_LINK(di, p0, p1, lnk_id) \
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_DSI_CMD_SHORT(di, p0, p1, lnk_id,\
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TEGRA_DSI_PACKET_CMD, CMD_NOT_CLUBBED)
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#define DSI_CMD_SHORT(di, p0, p1) \
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DSI_CMD_SHORT_LINK(di, p0, p1, TEGRA_DSI_LINK0)
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#define DSI_DLY_MS(ms) { \
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.cmd_type = TEGRA_DSI_DELAY_MS, \
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.sp_len_dly.delay_ms = ms, \
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}
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#define DSI_GPIO_SET(rst_gpio, on) { \
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.cmd_type = TEGRA_DSI_GPIO_SET, \
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.data_id = on, \
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.sp_len_dly.gpio = rst_gpio, \
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}
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#define _DSI_CMD_LONG(di, ptr, lnk_id, _cmd_type) { \
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.cmd_type = _cmd_type, \
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.data_id = di, \
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.sp_len_dly.data_len = ARRAY_SIZE(ptr), \
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.pdata = ptr, \
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.link_id = lnk_id, \
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}
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#define DSI_CMD_VBLANK_LONG(di, ptr) \
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_DSI_CMD_LONG(di, ptr, TEGRA_DSI_LINK0, \
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TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD)
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#define DSI_CMD_LONG_LINK(di, ptr, lnk_id) \
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_DSI_CMD_LONG(di, ptr, lnk_id, TEGRA_DSI_PACKET_CMD)
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#define DSI_CMD_LONG(di, ptr) \
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DSI_CMD_LONG_LINK(di, ptr, TEGRA_DSI_LINK0)
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#define _DSI_CMD_LONG_SIZE(di, ptr, size, lnk_id, _cmd_type) { \
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.cmd_type = _cmd_type, \
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.data_id = di, \
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.sp_len_dly.data_len = size, \
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.pdata = ptr, \
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.link_id = lnk_id, \
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}
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#define DSI_CMD_LONG_SIZE(di, ptr, size) \
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_DSI_CMD_LONG_SIZE(di, ptr, size, TEGRA_DSI_LINK0, TEGRA_DSI_PACKET_CMD)
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#define DSI_SEND_FRAME(cnt) { \
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.cmd_type = TEGRA_DSI_SEND_FRAME, \
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.sp_len_dly.frame_cnt = cnt, \
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}
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struct dsi_phy_timing_ns {
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u16 t_hsdexit_ns;
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u16 t_hstrail_ns;
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u16 t_datzero_ns;
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u16 t_hsprepare_ns;
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u16 t_clktrail_ns;
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u16 t_clkpost_ns;
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u16 t_clkzero_ns;
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u16 t_tlpx_ns;
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u16 t_clkprepare_ns;
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u16 t_clkpre_ns;
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u16 t_wakeup_ns;
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u16 t_taget_ns;
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u16 t_tasure_ns;
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u16 t_tago_ns;
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};
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enum {
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CMD_VS = 0x01,
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CMD_VE = 0x11,
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CMD_HS = 0x21,
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CMD_HE = 0x31,
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CMD_EOT = 0x08,
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CMD_NULL = 0x09,
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CMD_SHORTW = 0x15,
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CMD_BLNK = 0x19,
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CMD_LONGW = 0x39,
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CMD_RGB = 0x00,
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CMD_RGB_16BPP = 0x0E,
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CMD_RGB_18BPP = 0x1E,
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CMD_RGB_18BPPNP = 0x2E,
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CMD_RGB_24BPP = 0x3E,
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CMD_CMPR_PIXEL_STREAM = 0x0B,
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CMD_DSC_WRITE_START = 0x2C,
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CMD_DSC_WRITE_CONT = 0x3C,
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};
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enum {
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TEGRA_DSI_DISABLE,
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TEGRA_DSI_ENABLE,
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};
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#define PKT_ID0(id) ((((id) & 0x3f) << 3) | \
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(((TEGRA_DSI_ENABLE) & 0x1) << 9))
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#define PKT_LEN0(len) (((len) & 0x7) << 0)
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#define PKT_ID1(id) ((((id) & 0x3f) << 13) | \
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(((TEGRA_DSI_ENABLE) & 0x1) << 19))
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#define PKT_LEN1(len) (((len) & 0x7) << 10)
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#define PKT_ID2(id) ((((id) & 0x3f) << 23) | \
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(((TEGRA_DSI_ENABLE) & 0x1) << 29))
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#define PKT_LEN2(len) (((len) & 0x7) << 20)
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#define PKT_ID3(id) ((((id) & 0x3f) << 3) | \
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(((TEGRA_DSI_ENABLE) & 0x1) << 9))
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#define PKT_LEN3(len) (((len) & 0x7) << 0)
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#define PKT_ID4(id) ((((id) & 0x3f) << 13) | \
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(((TEGRA_DSI_ENABLE) & 0x1) << 19))
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#define PKT_LEN4(len) (((len) & 0x7) << 10)
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#define PKT_ID5(id) ((((id) & 0x3f) << 23) | \
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(((TEGRA_DSI_ENABLE) & 0x1) << 29))
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#define PKT_LEN5(len) (((len) & 0x7) << 20)
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#define PKT_LP (((TEGRA_DSI_ENABLE) & 0x1) << 30)
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#define NUMOF_PKT_SEQ 12
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enum {
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DSI_VS_0 = 0x0,
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DSI_VS_1 = 0x1,
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};
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/* Aggressiveness level of DSI suspend. The higher, the more aggressive. */
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#define DSI_NO_SUSPEND 0
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#define DSI_HOST_SUSPEND_LV0 1
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#define DSI_HOST_SUSPEND_LV1 2
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#define DSI_HOST_SUSPEND_LV2 3
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/*
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* DPD (deep power down) mode for dsi pads.
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* - Available for DSI_VS1 and later.
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* - Available for Non-DSI_GANGED.
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* Usually, DSIC/DSID pads' DPD for DSI_INSTANCE_0 and
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DSI/DSIB pads' DPD for DSI_INSTANCE_1 can be enabled, respectively,
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* but in SW, sometimes pins from one pad can be used by
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* more than one module, so it may be dependent on board design.
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* 0:A
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* 1:B
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* 2:C
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* 3:D
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*/
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#define DSI_DPD_EN(i) (1 << i)
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struct tegra_dsi_board_info {
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u32 platform_boardid;
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u32 platform_boardversion;
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u32 display_boardid;
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u32 display_boardversion;
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};
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struct tegra_dsi_out {
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u8 n_data_lanes; /* required */
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u8 pixel_format; /* required */
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u8 refresh_rate; /* required */
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u8 rated_refresh_rate;
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u8 panel_reset; /* required */
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u8 virtual_channel; /* required */
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u8 dsi_instance;
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u16 dsi_panel_rst_gpio;
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u16 dsi_panel_bl_en_gpio;
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u16 dsi_panel_bl_pwm_gpio;
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u16 even_odd_split_width;
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u8 controller_vs;
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bool panel_has_frame_buffer; /* required*/
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/* Deprecated. Use DSI_SEND_FRAME panel command instead. */
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bool panel_send_dc_frames;
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struct tegra_dsi_cmd *dsi_init_cmd; /* required */
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u16 n_init_cmd; /* required */
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struct tegra_dsi_cmd *dsi_early_suspend_cmd;
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u16 n_early_suspend_cmd;
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struct tegra_dsi_cmd *dsi_late_resume_cmd;
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u16 n_late_resume_cmd;
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struct tegra_dsi_cmd *dsi_postvideo_cmd;
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u16 n_postvideo_cmd;
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struct tegra_dsi_cmd *dsi_suspend_cmd; /* required */
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u16 n_suspend_cmd; /* required */
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u8 video_data_type; /* required */
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u8 video_clock_mode;
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u8 video_burst_mode;
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u8 ganged_type;
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u16 ganged_overlap;
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bool ganged_swap_links;
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bool ganged_write_to_all_links;
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u8 split_link_type;
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u8 suspend_aggr;
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u16 panel_buffer_size_byte;
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u16 panel_reset_timeout_msec;
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bool hs_cmd_mode_supported;
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bool hs_cmd_mode_on_blank_supported;
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bool enable_hs_clock_on_lp_cmd_mode;
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bool drm_override_disable;
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bool no_pkt_seq_eot; /* 1st generation panel may not
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* support eot. Don't set it for
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* most panels. */
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bool skip_dsi_pkt_header;
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bool te_polarity_low;
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bool power_saving_suspend;
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bool suspend_stop_stream_late;
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bool dsi2lvds_bridge_enable;
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bool dsi2edp_bridge_enable;
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u32 max_panel_freq_khz;
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u32 lp_cmd_mode_freq_khz;
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u32 lp_read_cmd_mode_freq_khz;
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u32 hs_clk_in_lp_cmd_mode_freq_khz;
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u32 burst_mode_freq_khz;
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u32 fpga_freq_khz;
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u32 te_gpio;
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u32 dpd_dsi_pads;
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const u32 *pkt_seq;
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struct dsi_phy_timing_ns phy_timing;
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u8 *bl_name;
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bool lp00_pre_panel_wakeup;
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bool ulpm_not_supported;
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struct tegra_dsi_board_info boardinfo;
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bool use_video_host_fifo_for_cmd;
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bool dsi_csi_loopback;
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bool set_max_timeout;
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u32 refresh_rate_adj;
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};
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struct tegra_panel_reg {
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struct regulator *avdd_lcd;
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struct regulator *avee_lcd;
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struct regulator *vddi_lcd;
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};
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enum {
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TEGRA_DC_STEREO_MODE_2D,
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TEGRA_DC_STEREO_MODE_3D
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};
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enum {
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TEGRA_DC_STEREO_LANDSCAPE,
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TEGRA_DC_STEREO_PORTRAIT
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};
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struct tegra_stereo_out {
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int mode_2d_3d;
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int orientation;
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void (*set_mode)(int mode);
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void (*set_orientation)(int orientation);
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};
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struct tegra_dc_mode {
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int pclk;
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int rated_pclk;
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int h_ref_to_sync;
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int v_ref_to_sync;
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int h_sync_width;
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int v_sync_width;
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int h_back_porch;
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int v_back_porch;
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int h_active;
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int v_active;
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int h_front_porch;
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int v_front_porch;
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int stereo_mode;
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|
u32 flags;
|
|
u8 avi_m;
|
|
u32 vmode;
|
|
bool pclk_hz_used;
|
|
};
|
|
|
|
struct tegra_dc_mode_metadata {
|
|
u64 line_in_nsec; /* Line duration in nsec */
|
|
int vtotal_lines; /* # of lines to vsync */
|
|
int vblank_lines; /* # of lines till vblank intr; vtotal-fp */
|
|
};
|
|
|
|
#define TEGRA_DC_MODE_FLAG_NEG_V_SYNC (1 << 0)
|
|
#define TEGRA_DC_MODE_FLAG_NEG_H_SYNC (1 << 1)
|
|
#define TEGRA_DC_MODE_FLAG_NEG_DE (1 << 2)
|
|
|
|
#define TEGRA_DC_MODE_AVI_M_NO_DATA 0x0
|
|
#define TEGRA_DC_MODE_AVI_M_4_3 0x1
|
|
#define TEGRA_DC_MODE_AVI_M_16_9 0x2
|
|
#define TEGRA_DC_MODE_AVI_M_64_27 0x3 /* dummy, no avi m support */
|
|
#define TEGRA_DC_MODE_AVI_M_256_135 0x4 /* dummy, no avi m support */
|
|
|
|
enum {
|
|
TEGRA_DC_OUT_RGB,
|
|
TEGRA_DC_OUT_HDMI,
|
|
TEGRA_DC_OUT_DSI,
|
|
TEGRA_DC_OUT_DP,
|
|
TEGRA_DC_OUT_LVDS,
|
|
TEGRA_DC_OUT_NVSR_DP,
|
|
TEGRA_DC_OUT_FAKE_DP,
|
|
TEGRA_DC_OUT_FAKE_DSIA,
|
|
TEGRA_DC_OUT_FAKE_DSIB,
|
|
TEGRA_DC_OUT_FAKE_DSI_GANGED,
|
|
TEGRA_DC_OUT_NULL,
|
|
TEGRA_DC_OUT_MAX /* Keep this always as last enum */
|
|
};
|
|
|
|
struct tegra_dc_out_pin {
|
|
int name;
|
|
int pol;
|
|
};
|
|
|
|
enum {
|
|
TEGRA_DC_OUT_PIN_DATA_ENABLE,
|
|
TEGRA_DC_OUT_PIN_H_SYNC,
|
|
TEGRA_DC_OUT_PIN_V_SYNC,
|
|
TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
|
|
};
|
|
|
|
enum {
|
|
TEGRA_DC_OUT_PIN_POL_LOW,
|
|
TEGRA_DC_OUT_PIN_POL_HIGH,
|
|
};
|
|
|
|
enum {
|
|
TEGRA_DC_UNDEFINED_DITHER = 0,
|
|
TEGRA_DC_DISABLE_DITHER,
|
|
TEGRA_DC_ORDERED_DITHER,
|
|
TEGRA_DC_ERRDIFF_DITHER,
|
|
TEGRA_DC_TEMPORAL_DITHER,
|
|
TEGRA_DC_ERRACC_DITHER,
|
|
};
|
|
|
|
typedef u8 tegra_dc_bl_output[256];
|
|
typedef u8 *p_tegra_dc_bl_output;
|
|
|
|
enum {
|
|
NO_CMD = 0x0,
|
|
ENABLE = 0x1,
|
|
DISABLE = 0x2,
|
|
PHASE_IN = 0x4,
|
|
AGG_CHG = 0x8,
|
|
};
|
|
|
|
enum {
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LHP0_LD21,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LHP1_LD18,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LHP2_LD19,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LVP0_LVP0_Out,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LVP1_LD20,
|
|
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1,
|
|
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LDI_LD22,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LPP_LD23,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LDC_SDC,
|
|
TEGRA_PIN_OUT_CONFIG_SEL_LSPI_DE,
|
|
};
|
|
|
|
/* this is the old name. provided for compatibility with old board files. */
|
|
#define dcc_bus ddc_bus
|
|
|
|
struct tegra_vrr {
|
|
s32 capability;
|
|
s32 enable;
|
|
s32 lastenable;
|
|
s32 flip;
|
|
s32 pclk;
|
|
s32 vrr_min_fps;
|
|
s32 vrr_max_fps;
|
|
s32 v_front_porch_max;
|
|
s32 v_front_porch_min;
|
|
s32 vfp_extend;
|
|
s32 vfp_shrink;
|
|
s32 v_front_porch;
|
|
s32 v_back_porch;
|
|
|
|
s64 curr_flip_us;
|
|
s64 last_flip_us;
|
|
s32 flip_count;
|
|
s32 flip_interval_us;
|
|
s32 frame_len_max;
|
|
s32 frame_len_min;
|
|
s32 frame_len_fluct;
|
|
s32 line_width;
|
|
s32 lines_per_frame_common;
|
|
|
|
s32 frame_type;
|
|
s32 frame_count;
|
|
s32 v_count;
|
|
s32 last_v_cnt;
|
|
s32 curr_v_cnt;
|
|
s64 last_frame_us;
|
|
s64 curr_frame_us;
|
|
s64 fe_time_us;
|
|
s32 frame_delta_us;
|
|
s32 frame_interval_us;
|
|
s32 even_frame_us;
|
|
s32 odd_frame_us;
|
|
|
|
s32 max_adj_pct;
|
|
s32 max_flip_pct;
|
|
s32 max_dcb;
|
|
s32 max_inc_pct;
|
|
|
|
s32 dcb;
|
|
s32 frame_avg_pct;
|
|
s32 fluct_avg_pct;
|
|
|
|
s32 fe_intr_req;
|
|
s32 db_tolerance;
|
|
s32 frame2flip_us;
|
|
s32 adjust_vfp;
|
|
s32 adjust_db;
|
|
u32 db_correct_cap;
|
|
u32 db_hist_cap;
|
|
s32 vfp;
|
|
s32 insert_frame;
|
|
|
|
/* Used with TLK */
|
|
s32 vrr_session_id;
|
|
/* Used with Trusty */
|
|
void *ta_ctx;
|
|
s32 nvdisp_direct_drive;
|
|
|
|
/* Must be kept in order */
|
|
u8 keynum;
|
|
u8 serial[9];
|
|
u8 challenge[32];
|
|
u8 digest[32];
|
|
u8 challenge_src;
|
|
};
|
|
|
|
struct tegra_dc_out {
|
|
int type;
|
|
unsigned flags;
|
|
unsigned hdcp_policy;
|
|
|
|
/* size in mm */
|
|
unsigned h_size;
|
|
unsigned v_size;
|
|
|
|
int ddc_bus;
|
|
int hotplug_gpio;
|
|
int hotplug_state; /* TEGRA_HPD_STATE_* */
|
|
int vrr_hotplug_state;
|
|
int prev_hotplug_state;
|
|
const char *parent_clk;
|
|
|
|
unsigned max_pixclock;
|
|
unsigned order;
|
|
unsigned align;
|
|
unsigned depth;
|
|
unsigned dither;
|
|
|
|
struct tegra_dc_mode *modes;
|
|
int n_modes;
|
|
|
|
struct tegra_dsi_out *dsi;
|
|
struct tegra_hdmi_out *hdmi_out;
|
|
struct tegra_dp_out *dp_out;
|
|
struct tegra_stereo_out *stereo;
|
|
struct tegra_vrr *vrr;
|
|
|
|
unsigned height; /* mm */
|
|
unsigned width; /* mm */
|
|
unsigned rotation; /* degrees */
|
|
|
|
struct tegra_dc_out_pin *out_pins;
|
|
unsigned n_out_pins;
|
|
|
|
/* DSI link compression parameters */
|
|
u32 slice_height;
|
|
u32 slice_width;
|
|
u8 num_of_slices;
|
|
u8 dsc_bpp;
|
|
bool en_block_pred;
|
|
bool dsc_en;
|
|
bool dual_dsc_en;
|
|
|
|
u8 *out_sel_configs;
|
|
unsigned n_out_sel_configs;
|
|
int user_needs_vblank;
|
|
struct completion user_vblank_comp;
|
|
|
|
bool is_ext_panel;
|
|
/* Default mode for fbconsole */
|
|
struct fb_videomode *fbcon_default_mode;
|
|
|
|
int (*enable)(struct device *);
|
|
int (*postpoweron)(struct device *);
|
|
int (*prepoweroff)(void);
|
|
int (*disable)(struct device *);
|
|
|
|
int (*hotplug_init)(struct device *);
|
|
int (*postsuspend)(void);
|
|
void (*hotplug_report)(bool);
|
|
};
|
|
|
|
/* bits for tegra_dc_out.flags */
|
|
#define TEGRA_DC_OUT_HOTPLUG_HIGH (0 << 1)
|
|
#define TEGRA_DC_OUT_HOTPLUG_LOW (1 << 1)
|
|
#define TEGRA_DC_OUT_HOTPLUG_MASK (1 << 1)
|
|
#define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON (0 << 2)
|
|
#define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND (1 << 2)
|
|
#define TEGRA_DC_OUT_NVHDCP_POLICY_MASK (1 << 2)
|
|
#define TEGRA_DC_OUT_CONTINUOUS_MODE (0 << 3)
|
|
#define TEGRA_DC_OUT_ONE_SHOT_MODE (1 << 3)
|
|
#define TEGRA_DC_OUT_N_SHOT_MODE (1 << 4)
|
|
#define TEGRA_DC_OUT_ONE_SHOT_LP_MODE (1 << 5)
|
|
#define TEGRA_DC_OUT_INITIALIZED_MODE (1 << 6)
|
|
/* Makes hotplug GPIO a LP0 wakeup source */
|
|
#define TEGRA_DC_OUT_HOTPLUG_WAKE_LP0 (1 << 7)
|
|
#define TEGRA_DC_OUT_NVSR_MODE (1 << 8)
|
|
|
|
#define TEGRA_DC_HDCP_POLICY_ALWAYS_ON 0
|
|
#define TEGRA_DC_HDCP_POLICY_ON_DEMAND 1
|
|
#define TEGRA_DC_HDCP_POLICY_ALWAYS_OFF 2
|
|
|
|
#define TEGRA_DC_ALIGN_MSB 0
|
|
#define TEGRA_DC_ALIGN_LSB 1
|
|
|
|
#define TEGRA_DC_ORDER_RED_BLUE 0
|
|
#define TEGRA_DC_ORDER_BLUE_RED 1
|
|
|
|
/* Errands use the interrupts */
|
|
#define V_BLANK_FLIP 0
|
|
#define V_BLANK_USER 2
|
|
#define V_BLANK_IMP 3
|
|
|
|
#define V_PULSE2_FLIP 0
|
|
#define V_PULSE2_LATENCY_MSRMNT 2
|
|
|
|
struct tegra_dc_cmu_csc {
|
|
u16 krr;
|
|
u16 kgr;
|
|
u16 kbr;
|
|
u16 krg;
|
|
u16 kgg;
|
|
u16 kbg;
|
|
u16 krb;
|
|
u16 kgb;
|
|
u16 kbb;
|
|
};
|
|
/* Currently, we are using tegra_dc_nvdisp_cmu only for parsing/using CMU data
|
|
* from device-tree
|
|
*/
|
|
struct tegra_dc_nvdisp_cmu {
|
|
u64 rgb[1025];
|
|
struct tegra_dc_nvdisp_win_csc panel_csc;
|
|
};
|
|
struct tegra_dc_cmu {
|
|
u16 lut1[256];
|
|
struct tegra_dc_cmu_csc csc;
|
|
u8 lut2[960];
|
|
};
|
|
|
|
struct tegra_dc_hdr {
|
|
bool enabled;
|
|
u32 eotf;
|
|
u32 static_metadata_id;
|
|
u8 static_metadata[24];
|
|
};
|
|
|
|
struct frame_lock_info {
|
|
bool frame_lock_enable;
|
|
bool job_pending;
|
|
bool check_for_error;
|
|
wait_queue_head_t win_upd_reqs;
|
|
|
|
};
|
|
|
|
#define TEGRA_WIN_PPFLAG_CP_ENABLE (1 << 0) /* enable RGB color lut */
|
|
#define TEGRA_WIN_PPFLAG_CP_FBOVERRIDE (1 << 1) /* override fbdev color lut */
|
|
|
|
struct tegra_fb_data {
|
|
int win;
|
|
|
|
int xres;
|
|
int yres;
|
|
int bits_per_pixel; /* -1 means autodetect */
|
|
size_t fbmem_size;
|
|
|
|
unsigned long flags;
|
|
};
|
|
|
|
#define TEGRA_FB_FLIP_ON_PROBE (1 << 0)
|
|
#define TEGRA_FB_WIN_INVALID -1
|
|
|
|
struct tegra_dc_platform_data {
|
|
unsigned long flags;
|
|
unsigned long emc_clk_rate;
|
|
struct tegra_dc_out *default_out;
|
|
struct tegra_fb_data *fb;
|
|
unsigned long low_v_win;
|
|
|
|
bool cmu_enable;
|
|
struct tegra_dc_cmu *cmu;
|
|
struct tegra_dc_nvdisp_cmu *nvdisp_cmu;
|
|
struct tegra_dc_cmu *cmu_adbRGB;
|
|
int default_clr_space;
|
|
unsigned long ctrl_num;
|
|
unsigned long win_mask;
|
|
struct device_node *conn_np; /* DSI, SOR0, SOR1, etc. */
|
|
struct device_node *panel_np; /* dp-display, hdmi-display etc. */
|
|
struct device_node *def_out_np; /* disp-default-out */
|
|
bool frame_lock_enable;
|
|
bool plld2_ss_enable;
|
|
};
|
|
|
|
struct tegra_dc_bw_data {
|
|
u32 total_bw;
|
|
u32 avail_bw;
|
|
u32 resvd_bw;
|
|
};
|
|
|
|
#define TEGRA_DC_FLAG_ENABLED (1 << 0)
|
|
#define TEGRA_DC_FLAG_SET_EARLY_MODE (1 << 1)
|
|
#define TEGRA_DC_FLAG_FBCON_DISABLED (1 << 2)
|
|
|
|
int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win);
|
|
struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win);
|
|
bool tegra_dc_get_connected(struct tegra_dc *);
|
|
bool tegra_dc_hpd(struct tegra_dc *dc);
|
|
|
|
bool tegra_dc_has_vsync(struct tegra_dc *dc);
|
|
int tegra_dc_vsync_enable(struct tegra_dc *dc);
|
|
void tegra_dc_vsync_disable(struct tegra_dc *dc);
|
|
int tegra_dc_wait_for_vsync(struct tegra_dc *dc);
|
|
void tegra_dc_blank_wins(struct tegra_dc *dc, unsigned windows);
|
|
int tegra_dc_restore(struct tegra_dc *dc);
|
|
|
|
void tegra_dc_enable(struct tegra_dc *dc);
|
|
void tegra_dc_disable(struct tegra_dc *dc);
|
|
int tegra_dc_set_default_videomode(struct tegra_dc *dc);
|
|
|
|
|
|
u32 tegra_dc_get_syncpt_id(struct tegra_dc *dc, int i);
|
|
u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i);
|
|
void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val);
|
|
struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val);
|
|
|
|
/* needed for tegra/dc/ext/ */
|
|
|
|
int __init tegra_dc_ext_module_init(void);
|
|
void __exit tegra_dc_ext_module_exit(void);
|
|
|
|
struct tegra_dc_ext *tegra_dc_ext_register(struct platform_device *ndev,
|
|
struct tegra_dc *dc);
|
|
void tegra_dc_ext_unregister(struct tegra_dc_ext *dc_ext);
|
|
|
|
void tegra_dc_ext_enable(struct tegra_dc_ext *dc_ext);
|
|
int tegra_dc_ext_disable(struct tegra_dc_ext *dc_ext);
|
|
int tegra_dc_ext_restore(struct tegra_dc_ext *dc_ext);
|
|
|
|
int tegra_dc_ext_process_hotplug(int output);
|
|
int tegra_dc_ext_process_vblank(int output, u64 timestamp);
|
|
int tegra_dc_ext_process_modechange(int output);
|
|
int tegra_dc_ext_process_bandwidth_renegotiate(int output,
|
|
struct tegra_dc_bw_data *bw);
|
|
bool tegra_dc_ext_is_userspace_active(void);
|
|
int tegra_dc_ext_get_scanline(struct tegra_dc_ext *dc_ext);
|
|
/* finish dc/ext */
|
|
|
|
#if defined(CONFIG_FRAMEBUFFER_CONSOLE)
|
|
bool fbcon_is_fgconsole(void);
|
|
#else
|
|
static inline bool fbcon_is_fgconsole(void)
|
|
{
|
|
return false;
|
|
}
|
|
#endif
|
|
|
|
/* needed for tegra_fb.h merge */
|
|
struct tegra_fb_info;
|
|
struct resource;
|
|
|
|
#if IS_ENABLED(CONFIG_FB_TEGRA)
|
|
int tegra_fb_redisplay_console(struct tegra_fb_info *tegra_info);
|
|
struct tegra_fb_info *tegra_fb_register(struct platform_device *ndev,
|
|
struct tegra_dc *dc,
|
|
struct tegra_fb_data *fb_data,
|
|
struct resource *fb_mem);
|
|
void tegra_fb_unregister(struct tegra_fb_info *fb_info);
|
|
void tegra_fb_pan_display_reset(struct tegra_fb_info *fb_info);
|
|
void tegra_fb_update_monspecs(struct tegra_fb_info *fb_info,
|
|
struct fb_monspecs *specs,
|
|
bool (*mode_filter)(const struct tegra_dc *dc,
|
|
struct fb_videomode *mode));
|
|
void tegra_fb_update_fix(struct tegra_fb_info *fb_info,
|
|
struct fb_monspecs *specs);
|
|
struct fb_var_screeninfo *tegra_fb_get_var(struct tegra_fb_info *fb_info);
|
|
int tegra_fb_create_sysfs(struct device *dev);
|
|
void tegra_fb_remove_sysfs(struct device *dev);
|
|
int tegra_fb_set_var(struct tegra_dc *dc, struct fb_var_screeninfo *var);
|
|
int tegra_fb_update_modelist(struct tegra_dc *dc, int fblistindex);
|
|
struct tegra_dc_win *tegra_fb_get_win(struct tegra_fb_info *tegra_fb);
|
|
struct tegra_dc_win *tegra_fb_get_blank_win(struct tegra_fb_info *tegra_fb);
|
|
int tegra_fb_set_win_index(struct tegra_dc *dc, unsigned long win_mask);
|
|
struct fb_videomode *tegra_fb_get_mode(struct tegra_dc *dc);
|
|
void tegra_fbcon_set_fb_mode(struct tegra_fb_info *fb_info,
|
|
struct fb_videomode *mode);
|
|
int tegra_fb_release_fbmem(struct tegra_fb_info *info);
|
|
#else
|
|
int tegra_fb_redisplay_console(struct tegra_fb_info *tegra_info)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
|
|
static inline struct tegra_fb_info *tegra_fb_register(
|
|
struct platform_device *ndev, struct tegra_dc *dc,
|
|
struct tegra_fb_data *fb_data, struct resource *fb_mem)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline void tegra_fb_unregister(struct tegra_fb_info *fb_info)
|
|
{
|
|
}
|
|
|
|
static inline void tegra_fb_pan_display_reset(struct tegra_fb_info *fb_info)
|
|
{
|
|
}
|
|
|
|
static inline void tegra_fb_update_monspecs(struct tegra_fb_info *fb_info,
|
|
struct fb_monspecs *specs,
|
|
bool (*mode_filter)(struct fb_videomode *mode))
|
|
{
|
|
}
|
|
|
|
static inline void tegra_fb_update_fix(struct tegra_fb_info *fb_info,
|
|
struct fb_monspecs *specs)
|
|
{
|
|
}
|
|
|
|
static inline struct fb_var_screeninfo *tegra_fb_get_var
|
|
(struct tegra_fb_info *fb_info)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline int tegra_fb_create_sysfs(struct device *dev)
|
|
{
|
|
return -ENOENT;
|
|
}
|
|
|
|
static inline void tegra_fb_remove_sysfs(struct device *dev)
|
|
{
|
|
}
|
|
|
|
static inline struct tegra_dc_win *tegra_fb_get_win(
|
|
struct tegra_fb_info *tegra_fb)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline struct tegra_dc_win *tegra_fb_get_blank_win(
|
|
struct tegra_fb_info *tegra_fb)
|
|
{
|
|
return NULL;
|
|
|
|
}
|
|
|
|
static inline struct fb_videomode *tegra_fb_get_mode(struct tegra_dc *dc)
|
|
{
|
|
return NULL;
|
|
}
|
|
static inline int tegra_fb_set_win_index
|
|
(struct tegra_dc *dc, unsigned long win_mask)
|
|
{
|
|
return 0;
|
|
}
|
|
void tegra_fbcon_set_fb_mode(struct tegra_fb_info *fb_info,
|
|
struct fb_videomode *mode)
|
|
{
|
|
}
|
|
static inline int tegra_fb_release_fbmem(struct tegra_fb_info *info)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
/* finish merge */
|
|
|
|
/* tegra_dc_update_windows and tegra_dc_sync_windows do not support windows
|
|
* with differenct dcs in one call
|
|
* dirty_rect is u16[4]: xoff, yoff, width, height
|
|
*/
|
|
int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n,
|
|
u16 *dirty_rect, bool wait_for_vblank, bool lock_flip);
|
|
int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n);
|
|
void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win);
|
|
int tegra_dc_attach_win(struct tegra_dc *dc, unsigned idx);
|
|
int tegra_dc_dettach_win(struct tegra_dc *dc, unsigned idx);
|
|
int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable);
|
|
bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts);
|
|
bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts);
|
|
|
|
int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode);
|
|
struct fb_videomode;
|
|
int tegra_dc_to_fb_videomode(struct fb_videomode *fbmode,
|
|
const struct tegra_dc_mode *mode);
|
|
int tegra_dc_set_fb_mode(struct tegra_dc *dc, const struct fb_videomode *fbmode,
|
|
bool stereo_mode);
|
|
|
|
unsigned tegra_dc_get_out_height(const struct tegra_dc *dc);
|
|
unsigned tegra_dc_get_out_width(const struct tegra_dc *dc);
|
|
unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc);
|
|
bool tegra_dc_valid_pixclock(const struct tegra_dc *dc,
|
|
const struct fb_videomode *mode);
|
|
|
|
#if defined(CONFIG_TEGRA_HDMIVRR) && (defined(CONFIG_TRUSTED_LITTLE_KERNEL) || defined(CONFIG_TRUSTY))
|
|
void tegra_hdmivrr_te_vrr_sec(struct tegra_vrr *vrr);
|
|
void tegra_hdmivrr_te_vrr_auth(struct tegra_vrr *vrr);
|
|
#endif
|
|
|
|
/* PM0 and PM1 signal control */
|
|
#define TEGRA_PWM_PM0 0
|
|
#define TEGRA_PWM_PM1 1
|
|
|
|
struct tegra_dc_pwm_params {
|
|
int which_pwm;
|
|
int gpio_conf_to_sfio;
|
|
unsigned int period;
|
|
unsigned int clk_div;
|
|
unsigned int clk_select;
|
|
unsigned int duty_cycle;
|
|
};
|
|
|
|
void tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg);
|
|
|
|
int tegra_dsi_send_panel_short_cmd(struct tegra_dc *dc, u8 *pdata, u8 data_len);
|
|
|
|
int __attribute__((weak)) tegra_nvdisp_update_win_csc(struct tegra_dc *dc,
|
|
int win_index);
|
|
int tegra_dc_update_win_csc(struct tegra_dc *dc, int win_index);
|
|
|
|
int tegra_dc_update_lut(struct tegra_dc *dc, int win_index, int fboveride);
|
|
int __attribute__((weak)) tegra_dc_update_nvdisp_lut(struct tegra_dc *dc,
|
|
int win_index, int fboveride);
|
|
|
|
/*
|
|
* In order to get a dc's current EDID, first call tegra_dc_get_edid() from an
|
|
* interruptible context. The returned value (if non-NULL) points to a
|
|
* snapshot of the current state; after copying data from it, call
|
|
* tegra_dc_put_edid() on that pointer. Do not dereference anything through
|
|
* that pointer after calling tegra_dc_put_edid().
|
|
*/
|
|
struct tegra_dc_edid {
|
|
size_t len;
|
|
u8 buf[0];
|
|
};
|
|
struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc);
|
|
void tegra_dc_put_edid(struct tegra_dc_edid *edid);
|
|
|
|
int tegra_dc_get_head(const struct tegra_dc *dc);
|
|
int tegra_dc_get_out(const struct tegra_dc *dc);
|
|
int tegra_dc_get_source_physical_address(u8 *phy_address);
|
|
|
|
bool tegra_is_bl_display_initialized(int instance);
|
|
|
|
static inline void find_dc_node(struct device_node **dc1_node,
|
|
struct device_node **dc2_node)
|
|
{
|
|
pr_err("%s: function is unimplemented\n", __func__);
|
|
}
|
|
|
|
static inline struct tegra_dc *tegra_get_dc_from_dev(struct device *dev)
|
|
{
|
|
return platform_get_drvdata(container_of(dev,
|
|
struct platform_device, dev));
|
|
}
|
|
|
|
void tegra_dc_shutdown(struct platform_device *ndev);
|
|
|
|
void tegra_get_fb_resource(struct resource *fb_res, int instance);
|
|
|
|
unsigned tegra_dc_out_flags_from_dev(struct device *dev);
|
|
bool tegra_dc_initialized(struct device *dev);
|
|
bool tegra_dc_is_ext_panel(const struct tegra_dc *dc);
|
|
|
|
struct spd_infoframe {
|
|
u8 vendor_name[8];
|
|
u8 prod_desc[16];
|
|
u8 source_information;
|
|
};
|
|
|
|
struct tegra_hdmi_out {
|
|
bool hdmi2fpd_bridge_enable;
|
|
bool hdmi2gmsl_bridge_enable;
|
|
bool hdmi2dsi_bridge_enable;
|
|
u8 generic_infoframe_type;
|
|
struct spd_infoframe *spd_infoframe;
|
|
};
|
|
|
|
enum {
|
|
DRIVE_CURRENT_L0 = 0,
|
|
DRIVE_CURRENT_L1 = 1,
|
|
DRIVE_CURRENT_L2 = 2,
|
|
DRIVE_CURRENT_L3 = 3,
|
|
};
|
|
|
|
enum {
|
|
PRE_EMPHASIS_L0 = 0,
|
|
PRE_EMPHASIS_L1 = 1,
|
|
PRE_EMPHASIS_L2 = 2,
|
|
PRE_EMPHASIS_L3 = 3,
|
|
};
|
|
|
|
enum {
|
|
POST_CURSOR2_L0 = 0,
|
|
POST_CURSOR2_L1 = 1,
|
|
POST_CURSOR2_L2 = 2,
|
|
POST_CURSOR2_L3 = 3,
|
|
};
|
|
|
|
struct tegra_dc_dp_lt_settings {
|
|
u32 drive_current[4]; /* Entry for each lane */
|
|
u32 lane_preemphasis[4]; /* Entry for each lane */
|
|
u32 post_cursor[4]; /* Entry for each lane */
|
|
u32 tx_pu;
|
|
u32 load_adj;
|
|
};
|
|
|
|
enum {
|
|
DP_VS = 0,
|
|
DP_PE = 1,
|
|
DP_PC = 2,
|
|
DP_TX_PU = 3,
|
|
};
|
|
|
|
struct tegra_dc_lt_data {
|
|
u32 data[4][4][4];
|
|
const char *name;
|
|
};
|
|
|
|
struct tegra_dc_extcon_cable {
|
|
struct mutex lock;
|
|
struct completion comp;
|
|
struct notifier_block nb;
|
|
struct extcon_dev *edev;
|
|
void *drv_data;
|
|
bool connected;
|
|
};
|
|
|
|
struct tegra_dp_out {
|
|
struct tegra_dc_dp_lt_settings *lt_settings;
|
|
int n_lt_settings;
|
|
bool tx_pu_disable;
|
|
bool enhanced_framing_disable;
|
|
bool pc2_disabled;
|
|
int lanes;
|
|
u8 link_bw;
|
|
bool hdmi2fpd_bridge_enable;
|
|
int edp2lvds_i2c_bus_no;
|
|
bool edp2lvds_bridge_enable;
|
|
struct tegra_dc_lt_data *lt_data;
|
|
int n_lt_data;
|
|
struct tegra_dc_extcon_cable typec_ecable;
|
|
};
|
|
|
|
/*
|
|
* On T18x, isohub is the only memclient that's relevant to display.
|
|
* The following structs keep track of its isoclient info.
|
|
*/
|
|
struct nvdisp_bandwidth_config {
|
|
u32 iso_bw; /* KB/s */
|
|
u32 total_bw; /* KB/s */
|
|
u32 emc_la_floor; /* Hz */
|
|
u32 hubclk; /* Hz */
|
|
};
|
|
|
|
struct nvdisp_isoclient_bw_info {
|
|
tegra_isomgr_handle isomgr_handle;
|
|
struct tegra_bwmgr_client *bwmgr_handle;
|
|
|
|
struct nvdisp_bandwidth_config max_config;
|
|
struct nvdisp_bandwidth_config cur_config;
|
|
|
|
u32 available_bw; /* KB/s */
|
|
u32 reserved_bw; /* KB/s */
|
|
|
|
u32 emc_at_res_bw; /* Hz */
|
|
u32 hubclk_at_res_bw; /* Hz */
|
|
};
|
|
|
|
struct nvdisp_imp_table {
|
|
struct tegra_nvdisp_imp_settings *settings;
|
|
u8 num_settings;
|
|
struct tegra_nvdisp_imp_settings *boot_setting;
|
|
};
|
|
|
|
|
|
/* Timestamp in nsec in TSC timebase */
|
|
u64 tegra_dc_get_tsc_time(void);
|
|
|
|
void tegra_dc_crc_deinit(struct tegra_dc *dc);
|
|
void tegra_dc_crc_drop_ref_cnts(struct tegra_dc *dc);
|
|
void tegra_dc_crc_reset(struct tegra_dc *dc);
|
|
int tegra_dc_crc_process(struct tegra_dc *dc);
|
|
|
|
/* APIs related to ring buffer */
|
|
struct tegra_dc_ring_buf;
|
|
void tegra_dc_ring_buf_add(struct tegra_dc_ring_buf *buf, void *src,
|
|
char **in_buf_ptr);
|
|
|
|
/* APIs related to CRC IOCTLs */
|
|
long tegra_dc_crc_enable(struct tegra_dc *dc, struct tegra_dc_ext_crc_arg *arg);
|
|
long tegra_dc_crc_disable(struct tegra_dc *dc,
|
|
struct tegra_dc_ext_crc_arg *arg);
|
|
long tegra_dc_crc_get(struct tegra_dc *dc, struct tegra_dc_ext_crc_arg *arg);
|
|
|
|
#endif
|