140 lines
5.6 KiB
C
140 lines
5.6 KiB
C
/*
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* dsi_padctrl.h: dsi padcontrol register definitions.
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION, All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define DSI_PADCTRL_GLOBAL_CNTRLS 0x2
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#define DSI_PADCTRL_PDVCLAMP_CD BIT(4)
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#define DSI_PADCTRL_PDVCLAMP_AB BIT(3)
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#define DSI_PADCTRL_PWR_DOWN_PD_IO_1_EN BIT(2)
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#define DSI_PADCTRL_PWR_DOWN_PD_IO_0_EN BIT(1)
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#define DSI_PADCTRL_PWR_DOWN_PD_CLK_EN BIT(0)
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#define DSI_PADCTRL_PWR_DOWN_MASK (DSI_PADCTRL_PWR_DOWN_PD_IO_1_EN | \
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DSI_PADCTRL_PWR_DOWN_PD_IO_0_EN | DSI_PADCTRL_PWR_DOWN_PD_CLK_EN)
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#define DSI_PADCTRL_A_LANES_PWR_DOWN 0x5
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#define DSI_PADCTRL_B_LANES_PWR_DOWN 0x11
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#define DSI_PADCTRL_C_LANES_PWR_DOWN 0x1D
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#define DSI_PADCTRL_D_LANES_PWR_DOWN 0x29
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#define DSI_PADCTRL_E_PULL_DWN_PD_IO_1_EN BIT(2)
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#define DSI_PADCTRL_E_PULL_DWN_PD_IO_0_EN BIT(1)
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#define DSI_PADCTRL_E_PULL_DWN_PD_CLK_EN BIT(0)
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#define DSI_PADCTRL_E_PULL_DWN_MASK (DSI_PADCTRL_E_PULL_DWN_PD_IO_1_EN | \
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DSI_PADCTRL_E_PULL_DWN_PD_IO_0_EN | DSI_PADCTRL_E_PULL_DWN_PD_CLK_EN)
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#define DSI_PADCTRL_A_PULL_DOWN 0x6
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#define DSI_PADCTRL_B_PULL_DOWN 0x12
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#define DSI_PADCTRL_C_PULL_DOWN 0x1E
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#define DSI_PADCTRL_D_PULL_DOWN 0x2A
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#define DSI_PADCTRL_INT_LP_BIAS_OVRRIDE_E_ATE_IO1_EN BIT(2)
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#define DSI_PADCTRL_INT_LP_BIAS_OVRRIDE_E_ATE_IO0_EN BIT(1)
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#define DSI_PADCTRL_INT_LP_BIAS_OVRRIDE_E_ATE_CLK_EN BIT(0)
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#define DSI_PADCTRL_A_INTERNAL_LP_BIAS_OVRRIDE 0x7
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#define DSI_PADCTRL_B_INTERNAL_LP_BIAS_OVRRIDE 0x13
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#define DSI_PADCTRL_C_INTERNAL_LP_BIAS_OVRRIDE 0x1F
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#define DSI_PADCTRL_D_INTERNAL_LP_BIAS_OVRRIDE 0x2B
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#define DSI_PADCTRL_DPHY_CLK_CONFIG_REV_CLK_EN BIT(0)
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#define DSI_PADCTRL_A_DPHY_CLK_CONFIG 0x8
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#define DSI_PADCTRL_B_DPHY_CLK_CONFIG 0x14
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#define DSI_PADCTRL_C_DPHY_CLK_CONFIG 0x20
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#define DSI_PADCTRL_D_DPHY_CLK_CONFIG 0x2C
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#define DSI_PADCTRL_VALID_OUTPUT_DELAY_TRIMMER_OUTADJ_IO1(x) (((x) & 0x3F) << 20)
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#define DSI_PADCTRL_VALID_OUTPUT_DELAY_TRIMMER_OUTADJ_IO0(x) (((x) & 0x3F) << 10)
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#define DSI_PADCTRL_VALID_OUTPUT_DELAY_TRIMMER_OUTADJ_CLK(x) ((x) & 0x3F)
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#define DSI_PADCTRL_A_OUTPUT_DELAY_TRIMMER 0x9
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#define DSI_PADCTRL_B_OUTPUT_DELAY_TRIMMER 0x15
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#define DSI_PADCTRL_C_OUTPUT_DELAY_TRIMMER 0x21
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#define DSI_PADCTRL_D_OUTPUT_DELAY_TRIMMER 0x2D
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#define DSI_PADCTRL_VALID_PEMPD_IO1(x) (((x) & 0x3) << 20)
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#define DSI_PADCTRL_VALID_PEMPD_IO0(x) (((x) & 0x3) << 16)
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#define DSI_PADCTRL_VALID_PEMPD_CLK(x) (((x) & 0x3) << 12)
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#define DSI_PADCTRL_VALID_PEMPU_IO1(x) (((x) & 0x3) << 8)
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#define DSI_PADCTRL_VALID_PEMPU_IO0(x) (((x) & 0x3) << 4)
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#define DSI_PADCTRL_VALID_PEMPU_CLK(x) ((x) & 0x3)
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#define DSI_PADCTRL_A_PRE_EMPHASIS 0xA
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#define DSI_PADCTRL_B_PRE_EMPHASIS 0x16
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#define DSI_PADCTRL_C_PRE_EMPHASIS 0x22
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#define DSI_PADCTRL_VALID_CPHY_MID_STR_TRIO1_CTRL_EN BIT(1)
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#define DSI_PADCTRL_VALID_CPHY_MID_STR_TRIO0_CTRL_EN BIT(0)
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#define DSI_PADCTRL_A_CPHY_MID_STRENGTH 0xB
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#define DSI_PADCTRL_B_CPHY_MID_STRENGTH 0x17
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#define DSI_PADCTRL_C_CPHY_MID_STRENGTH 0x23
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#define DSI_PADCTRL_D_CPHY_MID_STRENGTH 0x2F
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#define DSI_PADCTRL_VALID_IMP_CTRL_LP_DWN_ADJ_IO1(x) (((x) & 0xF) << 20)
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#define DSI_PADCTRL_VALID_IMP_CTRL_LP_DWN_ADJ_IO0(x) (((x) & 0xF) << 16)
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#define DSI_PADCTRL_VALID_IMP_CTRL_LP_DWN_ADJ_CLK(x) (((x) & 0xF) << 12)
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#define DSI_PADCTRL_VALID_IMP_CTRL_LP_UP_ADJ_IO1(x) (((x) & 0xF) << 8)
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#define DSI_PADCTRL_VALID_IMP_CTRL_LP_UP_ADJ_IO0(x) (((x) & 0xF) << 4)
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#define DSI_PADCTRL_VALID_IMP_CTRL_LP_UP_ADJ_CLK(x) ((x) & 0xF)
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#define DSI_PADCTRL_A_LP_DRVR_IMP_CTRL 0xC
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#define DSI_PADCTRL_B_LP_DRVR_IMP_CTRL 0x18
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#define DSI_PADCTRL_C_LP_DRVR_IMP_CTRL 0x24
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#define DSI_PADCTRL_D_LP_DRVR_IMP_CTRL 0x30
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#define DSI_PADCTRL_VALID_SLEW_DOWN_IO1(x) (((x) & 0xF) << 20)
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#define DSI_PADCTRL_VALID_SLEW_DOWN_IO0(x) (((x) & 0xF) << 16)
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#define DSI_PADCTRL_VALID_SLEW_DOWN_CLK(x) (((x) & 0xF) << 12)
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#define DSI_PADCTRL_VALID_SLEW_UP_IO1(x) (((x) & 0xF) << 8)
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#define DSI_PADCTRL_VALID_SLEW_UP_IO0(x) (((x) & 0xF) << 4)
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#define DSI_PADCTRL_VALID_SLEW_UP_CLK(x) ((x) & 0xF)
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#define DSI_PADCTRL_A_LP_DRVR_SLEW_RATE_CTRL 0xD
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#define DSI_PADCTRL_B_LP_DRVR_SLEW_RATE_CTRL 0x19
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#define DSI_PADCTRL_C_LP_DRVR_SLEW_RATE_CTRL 0x25
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#define DSI_PADCTRL_D_LP_DRVR_SLEW_RATE_CTRL 0x31
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#define DSI_PADCTRL_CONTENTION_DET_E_CD_IO1_EN BIT(2)
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#define DSI_PADCTRL_CONTENTION_DET_E_CD_IO0_EN BIT(1)
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#define DSI_PADCTRL_CONTENTION_DET_E_CD_CLK_EN BIT(0)
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#define DSI_PADCTRL_A_CONTENTION_DET_CTRL 0xE
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#define DSI_PADCTRL_B_CONTENTION_DET_CTRL 0x1A
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#define DSI_PADCTRL_C_CONTENTION_DET_CTRL 0x26
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#define DSI_PADCTRL_D_CONTENTION_DET_CTRL 0x32
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#define DSI_PADCTRL_CDN_IO1_DETECTED BIT(5)
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#define DSI_PADCTRL_CDP_IO1_DETECTED BIT(4)
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#define DSI_PADCTRL_CDN_IO0_DETECTED BIT(3)
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#define DSI_PADCTRL_CDP_IO0_DETECTED BIT(2)
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#define DSI_PADCTRL_CDN_CLK_DETECTED BIT(1)
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#define DSI_PADCTRL_CDP_CLK_DETECTED BIT(0)
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#define DSI_PADCTRL_A_CONTENTION_DET_STATUS 0XF
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#define DSI_PADCTRL_B_CONTENTION_DET_STATUS 0X1B
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#define DSI_PADCTRL_C_CONTENTION_DET_STATUS 0X27
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#define DSI_PADCTRL_D_CONTENTION_DET_STATUS 0X33
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#define DSI_PAPCTRL_VALID_SPARE_IO1(x) (((x) & 0xF) << 8)
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#define DSI_PAPCTRL_VALID_SPARE_IO0(x) (((x) & 0xF) << 4)
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#define DSI_PAPCTRL_VALID_SPARE_CLK(x) ((x) & 0xF)
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#define DSI_PADCTRL_A_SPARE_BITS 0x10
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#define DSI_PADCTRL_B_SPARE_BITS 0x1C
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#define DSI_PADCTRL_C_SPARE_BITS 0x28
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#define DSI_PADCTRL_D_SPARE_BITS 0x34
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