581 lines
16 KiB
C
581 lines
16 KiB
C
/*
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* Tegra Graphics Init for T186 Architecture Chips
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*
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* Copyright (c) 2014-2019, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <soc/tegra/chip-id.h>
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#include <linux/platform/tegra/emc_bwmgr.h>
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#include <soc/tegra/kfuse.h>
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#include <linux/platform/tegra/mc.h>
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#include "dev.h"
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#include "class_ids.h"
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#include "class_ids_t186.h"
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#include "t186.h"
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#include "host1x/host1x.h"
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#include "tsec/tsec.h"
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#include "flcn/flcn.h"
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#include "isp/isp.h"
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#include "isp/isp_isr_v2.h"
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#if defined(CONFIG_TEGRA_GRHOST_NVCSI)
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#include "nvcsi/nvcsi.h"
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#endif
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#include <video/vi4.h>
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#include "nvdec/nvdec.h"
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#include "hardware_t186.h"
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#include "nvhost_scale.h"
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#include "scale_emc.h"
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#include "chip_support.h"
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#include "streamid_regs.c"
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#include "cg_regs.c"
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#include "actmon_regs.c"
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#define HOST_EMC_FLOOR 204000000
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#define HOST_NVDEC_EMC_FLOOR 102000000
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/*
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* TODO: Move following functions to the corresponding files under
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* kernel-3.18 once kernel-t18x gets merged there. Until that
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* happens we can keep these here to avoid extensive amount of
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* added infra
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*/
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static inline u32 flcn_thi_sec(void)
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{
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return 0x00000038;
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}
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static inline u32 flcn_thi_sec_ch_lock(void)
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{
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return (1 << 8);
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}
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#if defined(CONFIG_TEGRA_GRHOST_TSEC)
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static int nvhost_tsec_t186_finalize_poweron(struct platform_device *dev)
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{
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/* Disable access to non-THI registers through channel */
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host1x_writel(dev, flcn_thi_sec(), flcn_thi_sec_ch_lock());
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return nvhost_tsec_finalize_poweron(dev);
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}
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#endif
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#if defined(CONFIG_TEGRA_GRHOST_NVENC) || defined(CONFIG_TEGRA_GRHOST_NVJPG) \
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|| defined(CONFIG_TEGRA_GRHOST_VIC)
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static int nvhost_flcn_t186_finalize_poweron(struct platform_device *dev)
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{
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/* Disable access to non-THI registers through channel */
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host1x_writel(dev, flcn_thi_sec(), flcn_thi_sec_ch_lock());
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return nvhost_flcn_finalize_poweron(dev);
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}
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#endif
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#if defined(CONFIG_TEGRA_GRHOST_NVDEC)
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static int nvhost_nvdec_t186_finalize_poweron(struct platform_device *dev)
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{
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int ret;
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ret = tegra_kfuse_enable_sensing();
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if (ret)
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return ret;
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/* Disable access to non-THI registers through channel */
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host1x_writel(dev, flcn_thi_sec(), flcn_thi_sec_ch_lock());
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ret = nvhost_nvdec_finalize_poweron(dev);
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tegra_kfuse_disable_sensing();
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return ret;
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}
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#endif
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static struct host1x_device_info host1x04_info = {
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.nb_channels = T186_NVHOST_NUMCHANNELS,
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.ch_base = 0,
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.ch_limit = T186_NVHOST_NUMCHANNELS,
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.nb_mlocks = NV_HOST1X_NB_MLOCKS,
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.initialize_chip_support = nvhost_init_t186_support,
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.nb_hw_pts = NV_HOST1X_SYNCPT_NB_PTS,
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.nb_pts = NV_HOST1X_SYNCPT_NB_PTS,
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.pts_base = 0,
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.pts_limit = NV_HOST1X_SYNCPT_NB_PTS,
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.syncpt_policy = SYNCPT_PER_CHANNEL_INSTANCE,
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.channel_policy = MAP_CHANNEL_ON_SUBMIT,
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.firmware_area_size = SZ_1M,
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.nb_actmons = 1,
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.dma_mask = DMA_BIT_MASK(40),
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};
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struct nvhost_device_data t18_host1x_info = {
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.clocks = {
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{"host1x", 102000000},
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{"actmon", UINT_MAX}
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},
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.can_powergate = false,
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.autosuspend_delay = 50,
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.private_data = &host1x04_info,
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.finalize_poweron = nvhost_host1x_finalize_poweron,
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.prepare_poweroff = nvhost_host1x_prepare_poweroff,
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.isolate_contexts = true,
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};
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struct nvhost_device_data t18_host1x_hv_info = {
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.clocks = {
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{"host1x", 102000000},
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{"actmon", UINT_MAX}
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},
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.can_powergate = false,
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.autosuspend_delay = 2000,
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.private_data = &host1x04_info,
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.finalize_poweron = nvhost_host1x_finalize_poweron,
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.prepare_poweroff = nvhost_host1x_prepare_poweroff,
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};
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static struct host1x_device_info host1xb04_info = {
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.nb_channels = T186_NVHOST_NUMCHANNELS,
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.ch_base = 0,
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.ch_limit = T186_NVHOST_NUMCHANNELS,
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.nb_mlocks = NV_HOST1X_NB_MLOCKS,
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.initialize_chip_support = nvhost_init_t186_support,
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.nb_hw_pts = NV_HOST1X_SYNCPT_NB_PTS,
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.nb_pts = NV_HOST1X_SYNCPT_NB_PTS,
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.pts_base = 0,
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.pts_limit = NV_HOST1X_SYNCPT_NB_PTS,
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.syncpt_policy = SYNCPT_PER_CHANNEL_INSTANCE,
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.channel_policy = MAP_CHANNEL_ON_SUBMIT,
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.firmware_area_size = SZ_1M,
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.dma_mask = DMA_BIT_MASK(40),
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};
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struct nvhost_device_data t18_host1xb_info = {
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.clocks = {
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{"host1x", UINT_MAX},
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{"actmon", UINT_MAX}
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},
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.private_data = &host1xb04_info,
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};
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#ifdef CONFIG_TEGRA_GRHOST_ISP
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struct nvhost_device_data t18_isp_info = {
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.num_channels = 1,
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.moduleid = NVHOST_MODULE_ISP,
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.class = NV_VIDEO_STREAMING_ISP_CLASS_ID,
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.modulemutexes = {NV_HOST1X_MLOCK_ID_ISP},
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.devfs_name = "isp",
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/* HACK: Mark as keepalive until 1188795 is fixed */
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.keepalive = true,
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.can_powergate = true,
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.autosuspend_delay = 500,
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.poweron_reset = true,
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.clocks = {
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{"isp", 768000000},
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},
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.finalize_poweron = nvhost_isp_t210_finalize_poweron,
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.prepare_poweroff = nvhost_isp_t124_prepare_poweroff,
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.hw_init = nvhost_isp_register_isr_v2,
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.ctrl_ops = &tegra_isp_ctrl_ops,
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.resource_policy = RESOURCE_PER_CHANNEL_INSTANCE,
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.serialize = 1,
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.push_work_done = 1,
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.vm_regs = {{0x50, true} },
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.mlock_timeout_factor = 10,
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};
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#endif
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#if defined(CONFIG_VIDEO_TEGRA_VI) || defined(CONFIG_VIDEO_TEGRA_VI_MODULE)
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struct nvhost_device_data t18_vi_info = {
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.devfs_name = "vi",
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.exclusive = true,
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.class = NV_VIDEO_STREAMING_VI_CLASS_ID,
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.modulemutexes = {NV_HOST1X_MLOCK_ID_VI},
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/* HACK: Mark as keepalive until 1188795 is fixed */
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.keepalive = true,
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.can_powergate = true,
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.autosuspend_delay = 500,
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.poweron_reset = true,
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.support_abort_on_close = true,
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.moduleid = NVHOST_MODULE_VI,
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.clocks = {
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{"vi", 408000000},
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{"nvcsi", 204000000, 0, 0, 0, true},
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{"nvcsilp", 204000000, 0, 0, 0, true},
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},
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.num_channels = 15,
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.prepare_poweroff = nvhost_vi4_prepare_poweroff,
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.finalize_poweron = nvhost_vi4_finalize_poweron,
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.busy = nvhost_vi4_busy,
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.idle = nvhost_vi4_idle,
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.reset = nvhost_vi4_reset,
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.vm_regs = {{0x4000 * 4, true},
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{0x8000 * 4, true},
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{0xc000 * 4, true},
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{0x10000 * 4, true},
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{0x14000 * 4, true},
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{0x18000 * 4, true},
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{0x1c000 * 4, true},
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{0x20000 * 4, true},
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{0x24000 * 4, true},
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{0x28000 * 4, true},
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{0x2c000 * 4, true},
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{0x30000 * 4, true} },
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.num_ppc = 8,
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.aggregate_constraints = nvhost_vi4_aggregate_constraints,
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.no_platform_dma_mask = true,
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};
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#endif
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#if defined(CONFIG_TEGRA_GRHOST_NVENC)
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struct nvhost_device_data t18_msenc_info = {
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.version = NVHOST_ENCODE_FLCN_VER(6, 1),
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.devfs_name = "msenc",
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.class = NV_VIDEO_ENCODE_NVENC_CLASS_ID,
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.modulemutexes = {NV_HOST1X_MLOCK_ID_NVENC},
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.can_powergate = true,
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.autosuspend_delay = 500,
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.clocks = {
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{"nvenc", UINT_MAX, 0, TEGRA_MC_CLIENT_MSENC},
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{"emc", HOST_EMC_FLOOR,
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NVHOST_MODULE_ID_EXTERNAL_MEMORY_CONTROLLER,
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0, TEGRA_BWMGR_SET_EMC_SHARED_BW}
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},
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.engine_cg_regs = t18x_nvenc_gating_registers,
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.engine_can_cg = true,
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.poweron_reset = true,
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.finalize_poweron = nvhost_flcn_t186_finalize_poweron,
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.moduleid = NVHOST_MODULE_MSENC,
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.num_channels = 1,
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.firmware_name = "nvhost_nvenc061.fw",
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.serialize = 1,
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.push_work_done = 1,
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.resource_policy = RESOURCE_PER_CHANNEL_INSTANCE,
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.vm_regs = {{0x30, true}, {0x34, false} },
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.transcfg_addr = 0x1844,
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.transcfg_val = 0x20,
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.bwmgr_client_id = TEGRA_BWMGR_CLIENT_MSENC,
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.isolate_contexts = true,
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.mlock_timeout_factor = 3,
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};
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#endif
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#if defined(CONFIG_TEGRA_GRHOST_NVDEC)
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struct nvhost_device_data t18_nvdec_info = {
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.version = NVHOST_ENCODE_NVDEC_VER(3, 0),
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.devfs_name = "nvdec",
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.modulemutexes = {NV_HOST1X_MLOCK_ID_NVDEC},
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.class = NV_NVDEC_CLASS_ID,
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.can_powergate = true,
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.autosuspend_delay = 500,
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.clocks = {
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{"nvdec", UINT_MAX, 0, TEGRA_MC_CLIENT_NVDEC},
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{"emc", HOST_NVDEC_EMC_FLOOR,
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NVHOST_MODULE_ID_EXTERNAL_MEMORY_CONTROLLER,
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0, TEGRA_BWMGR_SET_EMC_FLOOR}
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},
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.engine_cg_regs = t18x_nvdec_gating_registers,
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.engine_can_cg = true,
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.poweron_reset = true,
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.finalize_poweron = nvhost_nvdec_t186_finalize_poweron,
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.moduleid = NVHOST_MODULE_NVDEC,
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.ctrl_ops = &tegra_nvdec_ctrl_ops,
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.num_channels = 1,
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.serialize = 1,
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.push_work_done = 1,
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.resource_policy = RESOURCE_PER_CHANNEL_INSTANCE,
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.vm_regs = {{0x30, true}, {0x34, false} },
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.transcfg_addr = 0x2c44,
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.transcfg_val = 0x20,
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.bwmgr_client_id = TEGRA_BWMGR_CLIENT_NVDEC,
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.isolate_contexts = true,
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.mlock_timeout_factor = 3,
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};
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#endif
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#if defined(CONFIG_TEGRA_GRHOST_NVJPG)
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struct nvhost_device_data t18_nvjpg_info = {
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.version = NVHOST_ENCODE_FLCN_VER(1, 1),
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.devfs_name = "nvjpg",
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.modulemutexes = {NV_HOST1X_MLOCK_ID_NVJPG},
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.class = NV_NVJPG_CLASS_ID,
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.can_powergate = true,
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.autosuspend_delay = 500,
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.clocks = {
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{"nvjpg", UINT_MAX, 0, TEGRA_MC_CLIENT_NVJPG},
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{"emc", HOST_EMC_FLOOR,
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NVHOST_MODULE_ID_EXTERNAL_MEMORY_CONTROLLER,
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0, TEGRA_BWMGR_SET_EMC_SHARED_BW}
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},
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.engine_cg_regs = t18x_nvjpg_gating_registers,
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.engine_can_cg = true,
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.poweron_reset = true,
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.finalize_poweron = nvhost_flcn_t186_finalize_poweron,
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.moduleid = NVHOST_MODULE_NVJPG,
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.num_channels = 1,
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.firmware_name = "nvhost_nvjpg011.fw",
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.serialize = 1,
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.push_work_done = 1,
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.resource_policy = RESOURCE_PER_CHANNEL_INSTANCE,
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.vm_regs = {{0x30, true}, {0x34, false} },
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.transcfg_addr = 0x1444,
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.transcfg_val = 0x20,
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.bwmgr_client_id = TEGRA_BWMGR_CLIENT_NVJPG,
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.isolate_contexts = true,
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.mlock_timeout_factor = 3,
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.module_irq = 14,
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};
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#endif
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#if defined(CONFIG_TEGRA_GRHOST_TSEC)
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struct nvhost_device_data t18_tsec_info = {
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.num_channels = 1,
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.devfs_name = "tsec",
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.version = NVHOST_ENCODE_TSEC_VER(1, 0),
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.modulemutexes = {NV_HOST1X_MLOCK_ID_TSEC},
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.class = NV_TSEC_CLASS_ID,
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.clocks = {
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{"tsec", UINT_MAX, 0, TEGRA_MC_CLIENT_TSEC},
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{"emc", HOST_EMC_FLOOR,
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NVHOST_MODULE_ID_EXTERNAL_MEMORY_CONTROLLER,
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0, TEGRA_BWMGR_SET_EMC_FLOOR}
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},
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.engine_cg_regs = t18x_tsec_gating_registers,
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.engine_can_cg = true,
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.can_powergate = true,
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.autosuspend_delay = 500,
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.keepalive = true,
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.moduleid = NVHOST_MODULE_TSEC,
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.poweron_reset = true,
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.finalize_poweron = nvhost_tsec_t186_finalize_poweron,
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.prepare_poweroff = nvhost_tsec_prepare_poweroff,
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.serialize = 1,
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.push_work_done = 1,
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.resource_policy = RESOURCE_PER_CHANNEL_INSTANCE,
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.vm_regs = {{0x30, true}, {0x34, false} },
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.transcfg_addr = 0x1644,
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.transcfg_val = 0x20,
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.bwmgr_client_id = TEGRA_BWMGR_CLIENT_TSEC,
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.mlock_timeout_factor = 3,
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};
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struct nvhost_device_data t18_tsecb_info = {
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.num_channels = 1,
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.devfs_name = "tsecb",
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.version = NVHOST_ENCODE_TSEC_VER(1, 0),
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.modulemutexes = {NV_HOST1X_MLOCK_ID_TSECB},
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.class = NV_TSECB_CLASS_ID,
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.clocks = {
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{"tsecb", UINT_MAX, 0, TEGRA_MC_CLIENT_TSECB},
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{"emc", HOST_EMC_FLOOR,
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NVHOST_MODULE_ID_EXTERNAL_MEMORY_CONTROLLER,
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0, TEGRA_BWMGR_SET_EMC_FLOOR}
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},
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.engine_cg_regs = t18x_tsec_gating_registers,
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.engine_can_cg = true,
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.can_powergate = true,
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.autosuspend_delay = 500,
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.keepalive = true,
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.moduleid = NVHOST_MODULE_TSECB,
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.poweron_reset = true,
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.finalize_poweron = nvhost_tsec_t186_finalize_poweron,
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.prepare_poweroff = nvhost_tsec_prepare_poweroff,
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.serialize = 1,
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.push_work_done = 1,
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.resource_policy = RESOURCE_PER_CHANNEL_INSTANCE,
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.vm_regs = {{0x30, true}, {0x34, false} },
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.transcfg_addr = 0x1644,
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.transcfg_val = 0x20,
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.bwmgr_client_id = TEGRA_BWMGR_CLIENT_TSECB,
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.mlock_timeout_factor = 3,
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};
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#endif
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#if defined(CONFIG_TEGRA_GRHOST_VIC)
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struct nvhost_device_data t18_vic_info = {
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.num_channels = 1,
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.devfs_name = "vic",
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.clocks = {
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{"vic", UINT_MAX, 0},
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{"emc", HOST_EMC_FLOOR,
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NVHOST_MODULE_ID_EXTERNAL_MEMORY_CONTROLLER,
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0, TEGRA_BWMGR_SET_EMC_SHARED_BW},
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},
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.engine_cg_regs = t18x_vic_gating_registers,
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.engine_can_cg = true,
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.version = NVHOST_ENCODE_FLCN_VER(4, 0),
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.can_powergate = true,
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.autosuspend_delay = 500,
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.moduleid = NVHOST_MODULE_VIC,
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.poweron_reset = true,
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.modulemutexes = {NV_HOST1X_MLOCK_ID_VIC},
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.class = NV_GRAPHICS_VIC_CLASS_ID,
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.finalize_poweron = nvhost_flcn_t186_finalize_poweron,
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.prepare_poweroff = nvhost_flcn_prepare_poweroff,
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.flcn_isr = nvhost_flcn_common_isr,
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.init_class_context = nvhost_vic_init_context,
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.firmware_name = "vic04_ucode.bin",
|
|
.serialize = 1,
|
|
.push_work_done = 1,
|
|
.resource_policy = RESOURCE_PER_CHANNEL_INSTANCE,
|
|
.vm_regs = {{0x30, true}, {0x34, false} },
|
|
.transcfg_addr = 0x2044,
|
|
.transcfg_val = 0x20,
|
|
.bwmgr_client_id = TEGRA_BWMGR_CLIENT_VIC,
|
|
.scaling_init = nvhost_scale_emc_init,
|
|
.scaling_deinit = nvhost_scale_emc_deinit,
|
|
.scaling_post_cb = &nvhost_scale_emc_callback,
|
|
.actmon_regs = HOST1X_THOST_ACTMON_VIC,
|
|
.actmon_enabled = true,
|
|
.actmon_irq = 3,
|
|
.actmon_weight_count = 213,
|
|
.actmon_setting_regs = t18x_vic_actmon_registers,
|
|
.devfreq_governor = "userspace",
|
|
.freqs = {100000000, 200000000, 300000000,
|
|
400000000, 500000000, 600000000},
|
|
.isolate_contexts = true,
|
|
.mlock_timeout_factor = 3,
|
|
.module_irq = 1,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_TEGRA_GRHOST_NVCSI)
|
|
struct nvhost_device_data t18_nvcsi_info = {
|
|
.num_channels = 1,
|
|
.clocks = {
|
|
{"nvcsi", 204000000},
|
|
{"nvcsilp", 204000000},
|
|
},
|
|
.devfs_name = "nvcsi",
|
|
.modulemutexes = {NV_HOST1X_MLOCK_ID_NVCSI},
|
|
.class = NV_VIDEO_STREAMING_NVCSI_CLASS_ID,
|
|
.ctrl_ops = &tegra_nvcsi_ctrl_ops,
|
|
.can_powergate = true,
|
|
.autosuspend_delay = 500,
|
|
.finalize_poweron = nvcsi_finalize_poweron,
|
|
.prepare_poweroff = nvcsi_prepare_poweroff,
|
|
.poweron_reset = true,
|
|
.keepalive = true,
|
|
.serialize = 1,
|
|
.push_work_done = 1,
|
|
.no_platform_dma_mask = true,
|
|
};
|
|
#endif
|
|
|
|
#include "host1x/host1x_channel_t186.c"
|
|
|
|
static void t186_set_nvhost_chanops(struct nvhost_channel *ch)
|
|
{
|
|
if (!ch)
|
|
return;
|
|
|
|
ch->ops = host1x_channel_ops;
|
|
}
|
|
|
|
int nvhost_init_t186_channel_support(struct nvhost_master *host,
|
|
struct nvhost_chip_support *op)
|
|
{
|
|
op->nvhost_dev.set_nvhost_chanops = t186_set_nvhost_chanops;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void t186_remove_support(struct nvhost_chip_support *op)
|
|
{
|
|
kfree(op->priv);
|
|
op->priv = NULL;
|
|
}
|
|
|
|
static void t186_init_regs(struct platform_device *pdev, bool prod)
|
|
{
|
|
struct nvhost_gating_register *regs = t18x_host1x_gating_registers;
|
|
struct nvhost_streamid_mapping *map_regs = t18x_host1x_streamid_mapping;
|
|
|
|
while (regs->addr) {
|
|
if (prod)
|
|
host1x_hypervisor_writel(pdev, regs->addr, regs->prod);
|
|
else
|
|
host1x_hypervisor_writel(pdev, regs->addr,
|
|
regs->disable);
|
|
regs++;
|
|
}
|
|
|
|
while (map_regs->host1x_offset) {
|
|
host1x_hypervisor_writel(pdev,
|
|
map_regs->host1x_offset,
|
|
map_regs->client_offset);
|
|
host1x_hypervisor_writel(pdev,
|
|
map_regs->host1x_offset + sizeof(u32),
|
|
map_regs->client_limit);
|
|
map_regs++;
|
|
}
|
|
}
|
|
|
|
#include "host1x/host1x_cdma_t186.c"
|
|
#include "host1x/host1x_syncpt.c"
|
|
#include "host1x/host1x_syncpt_prot_t186.c"
|
|
#include "host1x/host1x_intr_t186.c"
|
|
#include "host1x/host1x_debug_t186.c"
|
|
#include "host1x/host1x_vm_t186.c"
|
|
#if defined(CONFIG_TEGRA_GRHOST_SCALE)
|
|
#include "host1x/host1x_actmon_t186.c"
|
|
#endif
|
|
|
|
int nvhost_init_t186_support(struct nvhost_master *host,
|
|
struct nvhost_chip_support *op)
|
|
{
|
|
int err;
|
|
|
|
op->soc_name = "tegra18x";
|
|
|
|
/* don't worry about cleaning up on failure... "remove" does it. */
|
|
err = nvhost_init_t186_channel_support(host, op);
|
|
if (err)
|
|
return err;
|
|
|
|
op->cdma = host1x_cdma_ops;
|
|
op->push_buffer = host1x_pushbuffer_ops;
|
|
op->debug = host1x_debug_ops;
|
|
op->nvhost_dev.load_gating_regs = t186_init_regs;
|
|
|
|
host->sync_aperture = host->aperture;
|
|
op->syncpt = host1x_syncpt_ops;
|
|
op->intr = host1x_intr_ops;
|
|
op->vm = host1x_vm_ops;
|
|
#if defined(CONFIG_TEGRA_GRHOST_SCALE)
|
|
op->actmon = host1x_actmon_ops;
|
|
#endif
|
|
|
|
/* WAR to bugs 200094901 and 200082771: enable protection
|
|
* only on silicon/emulation */
|
|
|
|
op->syncpt.reset = t186_syncpt_reset;
|
|
op->syncpt.mark_used = t186_syncpt_mark_used;
|
|
op->syncpt.mark_unused = t186_syncpt_mark_unused;
|
|
|
|
op->syncpt.mutex_owner = t186_syncpt_mutex_owner;
|
|
|
|
op->remove_support = t186_remove_support;
|
|
|
|
return 0;
|
|
}
|