129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _LINUX_TEGRA_MCE_H
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#define _LINUX_TEGRA_MCE_H
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/* NOTE:
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* For correct version validation, below two defines need to be
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* updated whenever there is a new ARI implementation.
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*/
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#define CUR_ARI_VER_MAJOR 1
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#define CUR_ARI_VER_MINOR 2
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enum {
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TEGRA_MCE_XOVER_C1_C6, /* Only valid for Denver */
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TEGRA_MCE_XOVER_CC1_CC6,
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TEGRA_MCE_XOVER_CC1_CC7,
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TEGRA_MCE_XOVER_MAX = TEGRA_MCE_XOVER_CC1_CC7
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};
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enum {
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TEGRA_MCE_CSTATS_CLEAR,
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TEGRA_MCE_CSTATS_ENTRIES_SC7,
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TEGRA_MCE_CSTATS_ENTRIES_SC4,
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TEGRA_MCE_CSTATS_ENTRIES_SC3,
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TEGRA_MCE_CSTATS_ENTRIES_SC2,
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TEGRA_MCE_CSTATS_ENTRIES_CCP3,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CC6,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CC7,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CC6,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CC7,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CORE0_C6,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CORE1_C6,
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/* RESV: 12-13 */
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TEGRA_MCE_CSTATS_ENTRIES_D15_CORE0_C7 = 14,
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TEGRA_MCE_CSTATS_ENTRIES_D15_CORE1_C7,
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/* RESV: 16-17 */
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TEGRA_MCE_CSTATS_ENTRIES_A57_CORE0_C7 = 18,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CORE1_C7,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CORE2_C7,
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TEGRA_MCE_CSTATS_ENTRIES_A57_CORE3_C7,
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TEGRA_MCE_CSTATS_LAST_ENTRY_D15_CORE0,
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TEGRA_MCE_CSTATS_LAST_ENTRY_D15_CORE1,
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/* RESV: 24-25 */
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TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE0,
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TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE1,
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TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE2,
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TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE3,
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TEGRA_MCE_CSTATS_MAX = TEGRA_MCE_CSTATS_LAST_ENTRY_A57_CORE3,
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};
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enum {
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TEGRA_MCE_ENUM_D15_CORE0,
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TEGRA_MCE_D15_CORE1,
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/* RESV: 2-3 */
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TEGRA_MCE_ENUM_A57_0 = 4,
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TEGRA_MCE_ENUM_A57_1,
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TEGRA_MCE_ENUM_A57_2,
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TEGRA_MCE_ENUM_A57_3,
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TEGRA_MCE_ENUM_MAX = TEGRA_MCE_ENUM_A57_3,
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};
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enum {
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TEGRA_MCE_FEATURE_CCP3,
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};
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/* MCA support */
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typedef union {
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struct {
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u8 cmd;
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u8 subidx;
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u8 idx;
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u8 inst;
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};
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struct {
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u32 low;
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u32 high;
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};
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u64 data;
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} mca_cmd_t;
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/* NOTE: These functions will return -ENOTSUPP if no implementation */
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int tegra_mce_enter_cstate(u32 state, u32 wake_time);
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int tegra_mce_update_cstate_info(u32 cluster, u32 ccplex, u32 system,
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u8 force, u32 wake_mask, bool valid);
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int tegra_mce_update_crossover_time(u32 type, u32 time);
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int tegra_mce_read_cstate_stats(u32 state, u64 *stats);
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int tegra_mce_write_cstate_stats(u32 state, u32 stats);
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int tegra_mce_is_sc7_allowed(u32 state, u32 wake, u32 *allowed);
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int tegra_mce_online_core(int cpu);
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int tegra_mce_cc3_ctrl(u32 ndiv, u32 vindex, u8 enable);
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int tegra_mce_echo_data(u32 data, int *matched);
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int tegra_mce_read_versions(u32 *major, u32 *minor);
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int tegra_mce_enum_features(u64 *features);
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int tegra_mce_read_uncore_mca(mca_cmd_t cmd, u64 *data, u32 *error);
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int tegra_mce_write_uncore_mca(mca_cmd_t cmd, u64 data, u32 *error);
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int tegra_mce_read_uncore_perfmon(u32 req, u32 *data);
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int tegra_mce_write_uncore_perfmon(u32 req, u32 data);
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int tegra_mce_enable_latic(void);
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int tegra_mce_write_dda_ctrl(u32 index, u64 value);
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int tegra_mce_read_dda_ctrl(u32 index, u64 *value);
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/* Tegra cache functions */
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int tegra_flush_cache_all(void);
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int tegra_flush_dcache_all(void *__maybe_unused unused);
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int tegra_clean_dcache_all(void *__maybe_unused unused);
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/* L3 cache ways read/write functions */
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int tegra_mce_read_l3_cache_ways(u64 *value);
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int tegra_mce_write_l3_cache_ways(u64 data, u64 *value);
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#endif /* _LINUX_TEGRA_MCE_H */
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