101 lines
3.7 KiB
Plaintext
101 lines
3.7 KiB
Plaintext
Embedded Memory Controller
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Properties:
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- name : Should be emc
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- #address-cells : Should be 1
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- #size-cells : Should be 0
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- compatible : Should contain "nvidia,tegra20-emc".
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- reg : Offset and length of the register set for the device
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- nvidia,use-ram-code : If present, the sub-nodes will be addressed
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and chosen using the ramcode board selector. If omitted, only one
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set of tables can be present and said tables will be used
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irrespective of ram-code configuration.
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Child device nodes describe the memory settings for different configurations and clock rates.
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Example:
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memory-controller@7000f400 {
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#address-cells = < 1 >;
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#size-cells = < 0 >;
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compatible = "nvidia,tegra20-emc";
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reg = <0x7000f4000 0x200>;
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}
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Embedded Memory Controller ram-code table
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If the emc node has the nvidia,use-ram-code property present, then the
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next level of nodes below the emc table are used to specify which settings
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apply for which ram-code settings.
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If the emc node lacks the nvidia,use-ram-code property, this level is omitted
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and the tables are stored directly under the emc node (see below).
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Properties:
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- name : Should be emc-tables
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- nvidia,ram-code : the binary representation of the ram-code board strappings
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for which this node (and children) are valid.
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Embedded Memory Controller configuration table
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This is a table containing the EMC register settings for the various
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operating speeds of the memory controller. They are always located as
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subnodes of the emc controller node.
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There are two ways of specifying which tables to use:
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* The simplest is if there is just one set of tables in the device tree,
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and they will always be used (based on which frequency is used).
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This is the preferred method, especially when firmware can fill in
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this information based on the specific system information and just
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pass it on to the kernel.
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* The slightly more complex one is when more than one memory configuration
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might exist on the system. The Tegra20 platform handles this during
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early boot by selecting one out of possible 4 memory settings based
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on a 2-pin "ram code" bootstrap setting on the board. The values of
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these strappings can be read through a register in the SoC, and thus
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used to select which tables to use.
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Properties:
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- name : Should be emc-table
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- compatible : Should contain "nvidia,tegra20-emc-table".
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- reg : either an opaque enumerator to tell different tables apart, or
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the valid frequency for which the table should be used (in kHz).
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- clock-frequency : the clock frequency for the EMC at which this
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table should be used (in kHz).
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- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
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for operation at the 'clock-frequency' setting.
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The order and contents of the registers are:
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RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
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WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
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PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
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TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
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ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
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ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
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CFG_CLKTRIM_1, CFG_CLKTRIM_2
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emc-table@166000 {
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reg = <166000>;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = < 166000 >;
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nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 >;
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};
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emc-table@333000 {
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reg = <333000>;
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compatible = "nvidia,tegra20-emc-table";
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clock-frequency = < 333000 >;
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nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0 0 0 0 0
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0 0 0 0 >;
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};
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