324 lines
12 KiB
Plaintext
324 lines
12 KiB
Plaintext
NVIDIA Tegra Power Management Controller (PMC)
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides following functionalies/configurations:
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- Power-gating controllers for SoC and CPU power-islands.
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- Low power modes of I/O pads.
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- IO pad voltage configurations based on IO rail voltage.
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For NVIDIA SoCs, starting with Tegra124 and beyond, IO pads support
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multi-level voltages and can operate at a nominal IO voltage of
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either 1.8V or 3.3V. NVIDIA Tegra210 and beyond needs to configure
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its IO pad voltage based on IO rail voltage by SW explicitly. Tegra124
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has HW detection mechanism for IO rail voltage.
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Required properties:
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- name : Should be pmc
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- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
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must contain "nvidia,tegra30-pmc". For Tegra114, must contain
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"nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
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Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
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above, where <chip> is tegra132.
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries:
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"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
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Optional properties:
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- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and then
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fed into the ARM GIC. The PMC is not involved in the detection or
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handling of this interrupt signal, merely its inversion.
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- nvidia,suspend-mode : The suspend mode that the platform should use.
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
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1 (LP1): CPU voltage off and DRAM in self-refresh
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2 (LP2): CPU voltage off
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
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- nvidia,core-pwr-req-active-high : Same as nvidia,core-power-req-active-high.
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
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is enabled.
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Required properties when nvidia,suspend-mode is specified:
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- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
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- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
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Core power good time in uS.
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- nvidia,core-pwr-off-time : Core power off time in uS.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
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The LP0 vector contains the warm boot code that is executed by AVP when
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
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processor and always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed from the deep
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Hardware-triggered thermal reset:
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On Tegra30, Tegra114 and Tegra124, if the 'i2c-thermtrip' subnode exists,
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hardware-triggered thermal reset will be enabled.
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Required properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,i2c-controller-id : ID of I2C controller to send poweroff command to. Valid values are
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described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0" of the
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Tegra K1 Technical Reference Manual.
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- nvidia,bus-addr : Bus address of the PMU on the I2C bus
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- nvidia,reg-addr : I2C register address to write poweroff command to
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- nvidia,reg-data : Poweroff command to write to PMU
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Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'):
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- nvidia,pinmux-id : Pinmux used by the hardware when issuing poweroff command.
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Defaults to 0. Valid values are described in section 12.5.2
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"Pinmux Support" of the Tegra4 Technical Reference Manual.
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Example:
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/ SoC dts including file
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <2000>;
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nvidia,cpu-pwr-off-time = <100>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <458>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
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};
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/ Tegra board dts file
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{
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...
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pmc@7000f400 {
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i2c-thermtrip {
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nvidia,i2c-controller-id = <4>;
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nvidia,bus-addr = <0x40>;
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nvidia,reg-addr = <0x36>;
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nvidia,reg-data = <0x2>;
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};
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};
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...
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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...
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};
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== I/O pad Low power and voltage configuration node ==
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NVIDIA Tegra124 supports the HW based IO rail voltage detection and when it
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detect any change in IO voltage, it configures the PMC IO pad for desired
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voltage. Hence, it is not required to provide any information from Device
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Tree for the IO pad configurations.
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NVIDIA Tegra210 and beyond does not have HW based IO rail detection and
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hence SW need to explicitly configure PMC IO pad voltage based on IO rail
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voltage.
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The DT bindings for configuring the low power state and voltage configuration
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of IO pads follow the same design as pinctrl DT bindings. Please refer
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<../../pinctrl/pinctrl-bindings.txt> for details of the common pinctrl
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bindings used by client devices, including the meaning of the phrase
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"pin configuration node".
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The DT property of the IO pads must be under the node of Tegra PMC node.
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Tegra's IO pads configuration nodes act as a container for an arbitrary
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number of subnodes. Each of these subnodes represents some desired
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configuration for an IO pads, or a list of IO pads. This configuration
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can include the low power enable/disable control.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content. Each subnode only affects those
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parameters that are explicitly listed. Unspecified is represented as an absent
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property,
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The IO pad voltage configuration are required if:
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- there is IO rail power supply connected to IO pad and default
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configuration of IO pads voltage is not matching with the IO rail i.e.
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bootloader has not done the required initialization for IO pad voltage.
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- dynamic switching of IO rail voltage is required like SD3.0 and hence
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configuration in IO pads voltage.
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Required subnode-properties:
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==========================
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- pins : An array of strings. Each string contains the name of an IO pads. Valid
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values for these names are listed below.
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Optional subnode-properties:
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==========================
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Following properties are supported from generic pin configuration explained
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in <../../pinctrl/pinctrl-bindings.txt>.
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- low-power-enable: enable low power mode.
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- low-power-disable: disable low power mode.
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- nvidia,power-source-voltage: Integer, tells the power source voltage levels.
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There is two possible values for this property defines in the
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<include/dt-binding/pinctrl/pinctrl-tegra-io-pad.h>
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TEGRA_IO_PAD_VOLTAGE_1800000UV for 1.8V
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TEGRA_IO_PAD_VOLTAGE_3300000UV for 3.3V
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This property is supported for Tegra210 and beyond. Also some IO pads
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support the multi-voltage level in their pins.
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Valid values for pin for Tegra124 are:
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audio, bb, cam, comp, csia, csib, csie, dsi, dsib, dsic, dsid, hdmi,
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hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
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pex-ctrl, sdmmc1, sdmmc3, sdmmc4, sys-ddc, uart, usb0, usb1, usb2,
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usb-bias
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Valid values for pin for Tegra210 are:
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audio, audio-hv, cam, csia, csib, csic, csid, csie, csif,
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dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2,
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gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2,
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pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0,
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usb1, usb2, usb3.
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The IO pads which support multi-level voltage for Tegra210 are:
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audio, audio-hv, cam, dbg, dmic, gpio, pex-ctrl, sdmmc1,
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sdmmc3, spi, spi-hv, uart.
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Valid values for pin for Tegra186 are:
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audio-hv, audio, ao-hv, cam, csia, csib, csic, csid, csie, csif,
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conn, dsi, dbg, dsib, dsic, dsid, dmic-hv, edp, hdmi-dp0, hdmi-dp1,
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mipi-bias, pex-ctrl, pex-clk-bias, pex-clk1, pex-clk2, pex-clk3,
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sdmmc1-hv, sdmmc2-hv, sdmmc3-hv, sdmmc4, spi, usb0, usb1, usb2, usb-bias,
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uart, hsic, ufs,
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The IO pads which support multi-level voltage for Tegra186 are:
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audio-hv, ao-hv, dbg, dmic-hv, sdmmc1-hv, sdmmc2-hv, sdmmc3-hv.
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Example:
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pmc@7000e400 {
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pinctrl-names = "default";
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pinctrl-0 = <&io_pad_default>;
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io_pad_default: common {
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audio-hv {
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pins = "audio-hv";
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low-power-disable;
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nvidia,power-source-voltage = <TEGRA_IO_PAD_VOLTAGE_3300000UV>;
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};
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gpio {
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pins = "gpio";
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low-power-disable;
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};
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audio {
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pins = "audio";
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low-power-enable;
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};
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};
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};
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From client for dynamic control:
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#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
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pmc@c360000 {
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sdmmc1_e_33V_enable: sdmmc1_e_33V_enable {
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sdmmc1 {
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pins = "sdmmc1-hv";
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nvidia,power-source-voltage = <TEGRA_IO_PAD_VOLTAGE_3300000UV>;
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};
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};
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sdmmc1_e_33V_disable: sdmmc1_e_33V_disable {
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sdmmc1 {
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pins = "sdmmc1-hv";
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nvidia,power-source-voltage = <TEGRA_IO_PAD_VOLTAGE_1800000UV>;
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};
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};
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};
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sdhci@3440000 {
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pinctrl-names = "sdmmc_e_33V_enable", "sdmmc_e_33V_disable";
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pinctrl-0 = <&sdmmc1_e_33V_enable>;
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pinctrl-1 = <&sdmmc1_e_33V_disable>;
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};
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Wake up events
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The PMC is the only device that can wake up the system from deep sleep
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mode (i.e. LP0). There are some wake up events in the PMC wake mask
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register that can be used to trigger PMC to wake up the system. The PMC
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wake mask register defines which devices or siganls can be the source to
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trigger the PMC waking up. If the devices support waking up the system
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from deep sleep mode, then it needs to describe a property for PMC wake
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up events. This property defines the usage.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,pmc-wakeup : <pmc_phandle event_type event_offset trigger_type>
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pmc_phandle: the phandle of PMC device tree node
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event_type: 0 = PMC_WAKE_TYPE_GPIO
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1 = PMC_WAKE_TYPE_EVENT
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event_offset: the offset of PMC wake mask register
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trigger_type: set 0 when event_type is PMC_WAKE_TYPE_GPIO
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if event_type is PMC_WAKE_TYPE_EVENT
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0 = PMC_TRIGGER_TYPE_NONE
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1 = PMC_TRIGGER_TYPE_RISING
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2 = PMC_TRIGGER_TYPE_FALLING
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4 = PMC_TRIGGER_TYPE_HIGH
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8 = PMC_TRIGGER_TYPE_LOW
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The assignments of event_type and trigger_type can be
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found in header file <dt-bindings/soc/tegra-pmc.h>.
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- #nvidia,wake-cells : should be 3
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Example:
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/ SoC dts including file
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pmc: pmc {
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compatible = "nvidia,tegra114-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 261>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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};
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/ Tegra board dts file
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{
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...
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pmc {
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...
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nvidia,suspend-mode = <0>;
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#nvidia,wake-cells = <3>;
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...
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};
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...
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pmic {
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...
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nvidia,pmc-wakeup = <&pmc
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PMC_WAKE_TYPE_EVENT 18 PMC_TRIGGER_TYPE_LOW>;
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...
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};
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...
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gpio-keys {
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power {
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...
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nvidia,pmc-wakeup = <&pmc
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PMC_WAKE_TYPE_GPIO 16 PMC_TRIGGER_TYPE_NONE>;
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...
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};
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};
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};
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