124 lines
5.2 KiB
Plaintext
124 lines
5.2 KiB
Plaintext
* Nvidia sdhci-tegra controller
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This file documents differences between the core properties in mmc.txt
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and the properties used by the sdhci-tegra driver.
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Required properties:
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- compatible: Should be "nvidia,tegra210-sdhci"
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- reg: Specify start address and registers count details
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- interrupts: Specify the interrupts IRQ info for device
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- id: Specify device id
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Optional properties:
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- built-in: Add the check if the device is built-in device
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- bus-width: Specify device bus width details
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- max-clk-limit: Specify the maximum clock limit for the device
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- ddr-clk-limit: Specify the maximum clock frequency in kHz for device in DDR mode
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- mmc-ocr-mask: Specify OCR register masking details
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- uhs-mask: Specify modes that are masked for the device
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Mask HS200 mode: 0x20
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Mask HS400 mode: 0x40
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Mask SDR104 mode: 0x10
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Mask SDR50 mode: 0x4
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Mask DDR50 mode: 0x8
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Mask SDR25 mode: 0x2
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- pll_source: Specify list of clock parents
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- dqs-trim-delay: HS400 Tap value for incoming DQS path trimmer.
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- cd-gpios: details of GPIO port used for SD card detect
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- wp-gpios: details of GPIO port used for SD card write protect mode
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- power-gpios: details of GPIO port used to power up SDIO card
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- default-drv-type: Drive strength to select for SDIO devices is encoded as 8-bit char as follows
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Drive strength Type B: 0x0
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Drive strength Type A: 0x1
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Drive strength Type C: 0x2
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Drive strength Type D: 0x3
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- disable-dynamic-clock-gating: flag when set disables sdmmc clock gating
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- nvidia,disable-rtpm: Set this flag to disable runtime power management
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support for sdhci devices.
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- power-off-rail: flag when set enables sdmmc reboot notifier
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- pwrdet-support: flag when set indicates the sdmmc controller instance needs power detect bit programming for voltage switching.
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- pwrdet-bit: Specify Tegra Power Management Controller power detect bit for the particular SDMMC controller instance. This field is specified only when the pwrdet-support is true
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- nvidia,is-emmc: Enable this flag for eMMC devices
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- nvidia,is-sdio: Enable this flag for SDIO devices
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- nvidia,sd-device: Enable this flag for SD devices
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- fixed-clock-freq: The first element is for ID mode. The rest of the entries are for different modes indexed as per ios timings.
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ID MODE 0
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MMC_TIMING_LEGACY 1
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MMC_TIMING_MMC_HS 2
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MMC_TIMING_SD_HS 3
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MMC_TIMING_UHS_SDR12 4
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MMC_TIMING_UHS_SDR25 5
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MMC_TIMING_UHS_SDR50 6
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MMC_TIMING_UHS_SDR104 7
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MMC_TIMING_UHS_DDR50 8
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MMC_TIMING_MMC_HS200 9
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MMC_TIMING_MMC_HS400 10
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- nvidia,enable-hwcq: Set this flag to enable HW Command Queue support.
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- nvidia,cd-wakeup-capable: Set this flag to enable card detect event as wake source.
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- nvidia,enable-strobe-mode: Enable enhance strobe mode when eMMC device runs at HS400 mode.
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- nvidia,en-periodic-calib: Enable periodic calibration support for sdmmc1/sdmmc3. Auto calibration sequence will be run at interval of 100ms during sdmmc1/sdmmc3 interfaces are active.
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- nvidia,parent_clk_list: Defines the list of parent clock corresponding to the speed mode.
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- nvidia,set-parent-clk: Use this flag, to select parent clock based on current speed mode, where parent-list available in DT.
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- nvidia,en-periodic-cflush: Set this flag to enable periodic cache flushing
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to improve write performance without overhead of flushing cache with every
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write.
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- force-non-removable-rescan: Set this flag to force rescan for non-removable
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devices. Used for SDIO devices to allow re-init during wifi module
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load/unload.
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- only-1-8-v: Set this flag to specify that only 1.8V IO voltage is supported
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and same should be configured by default.
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- nvidia,clk-en-before-freq-update: Set this flag to enable clock before
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updating clock frequency rate. This is needed for some SDMMC controller
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instances.
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-nvidia,min-tap-delay: Defines minimum tap delay in picoseconds seen on a SOC.
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This value is SOC specific and used to compute lowerthreshold, upperthreshold, fixed_tap values needed for post auto-tuning correction algorithm.
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-nvidia,max-tap-delay: Defines maximum tap delay in picoseconds seen on a SOC.
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This value is SOC specific and used to compute lowerthreshold, upperthreshold, fixed_tap values needed for post auto-tuning correction algorithm.
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Example:
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sdhci@700b0600 {
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compatible = "nvidia,tegra210-sdhci";
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reg = <0x0 0x700b0600 0x0 0x200>;
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interrupts = < 0 31 0x04 >;
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tap-delay = <4>;
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trim-delay = <3>;
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mmc-ocr-mask = <0>;
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max-clk-limit = <200000000>;
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uhs-mask = <0x20>; /* Mask HS200 */
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bus-width = <8>;
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id = <3>;
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pll_source = "pll_m", "pll_p";
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built-in;
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compad-vref-3v3 = <0x7>;
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compad-vref-1v8 = <0x7>;
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disable-dynamic-clock-gating;
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nvidia,runtime-pm-type = <1>;
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nvidia,en-periodic-cflush;
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nvidia,set-parent-clk;
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nvidia,enable-hwcq;
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nvidia,parent_clk_list = <"pll_p", "pll_c4_out0", "pll_p">;
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nvidia,min-tap-delay = <96>;
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nvidia,max-tap-delay = <139>;
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only-1-8-v;
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status = "okay";
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fixed-clock-freq = <25500000 25500000 24000000 47000000 24000000 47000000 94000000 204000000 0 0 0>;
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};
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sdhci@700b0000 {
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tap-delay = <0>;
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trim-delay = <2>;
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mmc-ocr-mask = <3>;
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max-clk-limit = <136000000>;
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ddr-clk-limit = <41000000>;
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uhs-mask = <0x8>;
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bus-width = <4>;
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id = <0>;
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pll_source = "pll_m", "pll_p";
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default-drive-type = <1>;
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force-non-removable-rescan;
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nvidia,min-tap-delay = <96>;
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nvidia,max-tap-delay = <139>;
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status = "okay";
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};
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