101 lines
4.1 KiB
Plaintext
101 lines
4.1 KiB
Plaintext
* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)
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Required properties:
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- compatible: Should be "snps,dwmac-<ip_version>" "snps,dwmac"
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For backwards compatibility: "st,spear600-gmac" is also supported.
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- reg: Address and length of the register set for the device
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- interrupt-parent: Should be the phandle for the interrupt controller
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that services interrupts for this device
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- interrupts: Should contain the STMMAC interrupts
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- interrupt-names: Should contain the interrupt names "macirq"
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"eth_wake_irq" if this interrupt is supported in the "interrupts"
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property
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- phy-mode: See ethernet.txt file in the same directory.
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- snps,reset-gpio gpio number for phy reset.
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- snps,reset-active-low boolean flag to indicate if phy reset is active low.
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- snps,reset-delays-us is triplet of delays
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The 1st cell is reset pre-delay in micro seconds.
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The 2nd cell is reset pulse in micro seconds.
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The 3rd cell is reset post-delay in micro seconds.
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Optional properties:
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- resets: Should contain a phandle to the STMMAC reset signal, if any
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- reset-names: Should contain the reset signal name "stmmaceth", if a
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reset phandle is given
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- max-frame-size: See ethernet.txt file in the same directory
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- clocks: If present, the first clock should be the GMAC main clock and
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the second clock should be peripheral's register interface clock. Further
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clocks may be specified in derived bindings.
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- clock-names: One name for each entry in the clocks property, the
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first one should be "stmmaceth" and the second one should be "pclk".
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- clk_ptp_ref: this is the PTP reference clock; in case of the PTP is
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available this clock is used for programming the Timestamp Addend Register.
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If not passed then the system clock will be used and this is fine on some
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platforms.
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- tx-fifo-depth: See ethernet.txt file in the same directory
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- rx-fifo-depth: See ethernet.txt file in the same directory
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- snps,pbl Programmable Burst Length
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- snps,aal Address-Aligned Beats
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- snps,fixed-burst Program the DMA to use the fixed burst mode
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- snps,mixed-burst Program the DMA to use the mixed burst mode
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- snps,force_thresh_dma_mode Force DMA to use the threshold mode for
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both tx and rx
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- snps,force_sf_dma_mode Force DMA to use the Store and Forward
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mode for both tx and rx. This flag is
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ignored if force_thresh_dma_mode is set.
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- snps,multicast-filter-bins: Number of multicast filter hash bins
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supported by this device instance
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- snps,perfect-filter-entries: Number of perfect filter entries supported
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by this device instance
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- snps,ps-speed: port selection speed that can be passed to the core when
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PCS is supported. For example, this is used in case of SGMII
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and MAC2MAC connection.
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- AXI BUS Mode parameters: below the list of all the parameters to program the
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AXI register inside the DMA module:
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- snps,lpi_en: enable Low Power Interface
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- snps,xit_frm: unlock on WoL
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- snps,wr_osr_lmt: max write outstanding req. limit
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- snps,rd_osr_lmt: max read outstanding req. limit
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- snps,kbbe: do not cross 1KiB boundary.
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- snps,axi_all: align address
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- snps,blen: this is a vector of supported burst length.
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- snps,fb: fixed-burst
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- snps,mb: mixed-burst
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- snps,rb: rebuild INCRx Burst
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- snps,tso: this enables the TSO feature otherwise it will be managed by
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MAC HW capability register.
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- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus.
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Examples:
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stmmac_axi_setup: stmmac-axi-config {
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snps,wr_osr_lmt = <0xf>;
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snps,rd_osr_lmt = <0xf>;
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snps,blen = <256 128 64 32 0 0 0>;
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};
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gmac0: ethernet@e0800000 {
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compatible = "st,spear600-gmac";
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reg = <0xe0800000 0x8000>;
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interrupt-parent = <&vic1>;
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interrupts = <24 23>;
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interrupt-names = "macirq", "eth_wake_irq";
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mac-address = [000000000000]; /* Filled in by U-Boot */
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max-frame-size = <3800>;
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phy-mode = "gmii";
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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rx-fifo-depth = <16384>;
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tx-fifo-depth = <16384>;
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clocks = <&clock>;
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clock-names = "stmmaceth";
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snps,axi-config = <&stmmac_axi_setup>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy1: ethernet-phy@0 {
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};
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};
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};
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