100 lines
3.6 KiB
Plaintext
100 lines
3.6 KiB
Plaintext
NVIDIA Tegra114 SPI controller.
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Required properties:
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- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
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Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
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<chip> is tegra124, tegra132, or tegra210.
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- reg: Should contain SPI registers location and length.
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- interrupts: Should contain SPI interrupts.
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- clock-names : Must include the following entries:
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- spi
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries:
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- spi
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- dmas : Must contain an entry for each entry in clock-names.
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See ../dma/dma.txt for details.
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- dma-names : Must include the following entries:
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- rx
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- tx
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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Recommended properties:
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- spi-max-frequency: Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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- cs-gpios: Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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Optional properties:
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- nvidia,clock-always-on : Enable clock of spi always.
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- nvidia,polling-mode : Use polling method instead of interrupts
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- nvidia,boost-reg-access : In T210 and earlier chips SPI register access
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is dependent on SPI clock frequency. Setting this option would
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allow SPI clock frequency to be boosted. Benefitial when running
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SPI at low frequencies with cpu based transfers. Default false.
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- nvidia,maximum-dma-buffer-size : Maximum dma buffer size per transfer.
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If this is not available then 16K will be default. The value should
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be unit of byte.
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spi-client device controller properties:
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Below properties should be defined under 'controller-data' child node
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- nvidia,enable-hw-based-cs : (Boolean) Use the HW based CS if enabled.
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- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device
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with this tap value.
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- nvidia,rx-clk-tap-delay : Delays the clock coming in from the external
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device with this tap value.
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- nvidia,cs-setup-clk-count : CS setup timing parameter.
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- nvidia,cs-hold-clk-count : CS hold timing parameter.
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- nvidia,cs-inactive-cycles : Cycles to be inactive between two packets.
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CS Inactive between packets is disabled if value of this is zero.
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- nvidia,clk-delay-between-packets : Clock delay between packets by keeping
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CS active. For this, it is required to pass the Chip select
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as GPIO.
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Production settings:
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Default settings that would apply during initialization. They can be
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chip specific or platform specific. These settings override trimmer and
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timing settings that would be provided with above properties. SPI prod
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settings are provided in below format.
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spi1@3210000 {
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prod-settings {
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prod {
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prod = <
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0x0 0x73fff83f 0x43c01807
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0xc 0x0000003f 0x00000020>;
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};
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prod_c_cs1 {
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prod = <
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0x4 0x00000fff 0x00000008
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0x8 0x0000ff00 0x00000000>;
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};
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};
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};
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- prod : settings that would apply to all client devices for specified
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controller.
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- prod_c_csX : settings applied on client csX when it is active.
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Refer to prod settings documentation on how reg/mask/value are provided.
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Care taken prod-settings which is a child of SPI controller is not
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treated as a SPI client.
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Example:
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spi@7000d600 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d600 0x200>;
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interrupts = <0 82 0x04>;
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spi-max-frequency = <25000000>;
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nvidia,clock-always-on;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 44>;
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clock-names = "spi";
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resets = <&tegra_car 44>;
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reset-names = "spi";
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dmas = <&apbdma 16>, <&apbdma 16>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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