242 lines
7.7 KiB
Plaintext
242 lines
7.7 KiB
Plaintext
NVIDIA Tegra210 QSPI(Quad Serial Peripheral Interface) controller.
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The NVIDIA Tegra210 QSPI controller is used to interface with various
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QSPI flashes/devices using the SPI communication interface.
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Required SOC specific properties:
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---------------------------------
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- compatible: Must be one of
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"nvidia,tegra210-qspi".
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"nvidia,tegra186-qspi".
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: The interrupt number of QSPI controller to the cpu. The
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interrupt specifier format depends on the interrupt controller.
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- dmas : Two or more DMA channel specifiers following the convention outlined
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in bindings/dma/dma.txt
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- dma-names: Names for the dma channels. There must be at least one channel
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named "tx" for transmit and named "rx" for receive.
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names : Must include the following entries:
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qspi: For QSPI controller clock.
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qspi_out: For QSPI output signal.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries:
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qspi
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Optional SoC specific properties:
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---------------------------------
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- nvidia,clock-always-on: Boolean, Enable clock of spi always for life of
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system. Absence of this property will make dynamic
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clock gating i.e. enable clock only when transfer
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is started and disable clock once transfer is done.
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- qspi-autosuspend-delay: delay in milliseconds for runtime suspend after
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device is idle. Larger delay would prevent frequent
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clk toggles but might consume slightly more power.
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When this property is not set, default delay is 3000.
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Set this value to less than 500 for power saving and
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above 2000 for better perf.
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Recommended SoC properties:
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----------------------
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- spi-max-frequency: Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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Required Board Specific Properties:
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----------------------------------
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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Optional Board Specific Properties:
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-----------------------------------
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- nvidia,clk-parents: Array of clock source to select the QSPI clock source
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parent. Tegra QSPI has more than one clock source. However, all clock source
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are not allowed to feed clocks to QSPI due to DVS restrictions. On this case,
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this property helps to find the best clock source to get the minimum clock
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error in requested clock frequency and actually set.
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QSPI Controller specific data in SPI slave nodes:
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-----------------------------------------------
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The spi slave nodes should provide the following information which is required
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by the spi controller. Below properties should be defined under 'controller-data'
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child node of the spi slave node.
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- nvidia,x1-len-limit: Integer, X1 Length limit.
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- nvidia,x1-bus-speed: Integer, X1 Bus speed.
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- nvidia,x1-dymmy-cycle: Integer, X1 dummy cycle.
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- nvidia,x4-bus-speed: Integer, X4 bus speed.
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- nvidia,x4-dymmy-cycle: Integer, X4 dummy cycle.
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- nvidia,x4-is-ddr: Integer, X4 is DDR?
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- nvidia,ctrl-bus-clk-ratio Integer, clock ratio bewteen ctrl & bus clk
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- nvidia,combined-seq-mode-en: Boolean, Select combined sequence mode.
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deprecated:
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- nvidia,ifddr-div2-sdr: Integer, If DDR then device by 2.
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Bus Speed:
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---------
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To maintain compatibility with old device tree, bus speed on interface is
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half of what is provided in device tree if property 'nvidia,ifddr-div2-sdr'
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is defined. Else speed maintained on interface is same as bus speed
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defined in device tree.
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QSPI contorller frequency is 2x of speed maintained at interface in DDR mode.
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For SDR mode, this can be set with 'cltrl-bus-clk-ratio'. Default is 2x (same
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as DDR mode) to avoid settings clock for each transaction and improve
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performance.
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Aliases:
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-------
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- All the QSPI/SPI controller nodes should be represented in the aliases
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node using the following format 'spi{n}' where n is a unique number for the alias.
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Prod Support:
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------------
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The recommended configuration for SoC/platform from HW/characterisation of
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SoC is provided as prod data. The POR value of controller registers may be
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different than this configurations. It is required to configure the
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controller registers with recommended setting before doing any data transfer.
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The prod setting from the SoC characterisation is provided under the
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sub-node "prod-settings". The prod data is provided under the sub node
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of "prod-settings" with different name (default and conditional) and
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it is used to configure controller register before starting transfer.
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The names of DT sub nodes for prod data are:
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- prod: Default DT node for prod setting which need to be configure before
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starting of any transfer.
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- prod_c_DDR<freq>: Conditional prod values for DDR mode of QSPI controller
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which will set with frequenncy "freq" in MHz. Like for:
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133MHz, the prod node name will be "prod_c_DDR133".
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100MHz, the prod node name will be "prod_c_DDR100".
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- prod_c_SDR<freq>: Conditional prod values for SDR mode of QSPI controller
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which will set with frequenncy "freq" in MHz. Like for:
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133MHz, the prod node name will be "prod_c_SDR133".
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100MHz, the prod node name will be "prod_c_SDR100".
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Example:
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- SoC Specific Portion:
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- For Tegra210:
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spi@70410000 {
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compatible = "nvidia,tegra210-qspi";
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reg = <0x0 0x70410000 0x0 0x1000>;
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interrupts = <0 10 0x04>;
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clocks = <&tegra_car TEGRA210_CLK_QSPI>,
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<&tegra_car TEGRA210_CLK_QSPI_OUT>;
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clock-names = "qspi","qspi_out";
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resets = <&tegra_car TEGRA186_RESET_QSPI>;
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reset-names = "qspi";
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dmas = <&apbdma 5>, <&apbdma 5>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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For Tegra186:
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spi@3270000 {
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compatible = "nvidia,tegra186-qspi";
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reg = <0x0 0x3270000 0x0 0x10000>;
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interrupts = < 0 35 0x04 >;
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dmas = <&gpcdma 5>, <&gpcdma 5>;
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dma-names = "rx", "tx";
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nvidia,clk-parents = "pll_p";
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clocks = <&tegra_car TEGRA186_CLK_QSPI>,
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<&tegra_car TEGRA186_CLK_QSPI_OUT>,
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<&tegra_car TEGRA186_CLK_PLLP_OUT0>,
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<&tegra_car TEGRA186_CLK_CLK_M>;
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clock-names = "qspi","qspi_out","pll_p","clk_m";
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resets = <&tegra_car TEGRA186_RESET_QSPI>;
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reset-names = "qspi";
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spi-max-frequency = <136000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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- Board Specific Portion:
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spi@3270000 {
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#address-cells = <1>;
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#size-cells = <0>;
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spi@0 {
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compatible = "spidev";
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reg = <1>;
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spi-max-frequency = <136000000>;
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controller-data {
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nvidia,x1-len-limit = <16>;
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nvidia,x1-bus-speed = <136000000>; /* In Mhz */
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nvidia,x1-dymmy-cycle = <0>;
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nvidia,x4-bus-speed = <136000000>;
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nvidia,x4-dymmy-cycle = <8>;
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nvidia,ifddr-div2-sdr = <1>;
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nvidia,x4-is-ddr;
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};
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};
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spiflash@1 {
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compatible = "s25fs512s";
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reg = <0>;
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spi-max-frequency = <136000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Whole_flash";
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reg = <0x00000000 0x4000000>;
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};
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controller-data {
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nvidia,x1-len-limit = <16>;
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nvidia,x1-bus-speed = <136000000>; /* In Mhz */
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nvidia,x1-dymmy-cycle = <8>;
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nvidia,x4-bus-speed = <136000000>;
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nvidia,x4-dymmy-cycle = <8>;
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nvidia,ifddr-div2-sdr = <1>;
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nvidia,x4-is-ddr;
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};
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};
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};
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- Prod setting porting
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spi@3270000 {
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prod-settings {
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#prod-cells = <3>;
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prod {
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prod = <0x000000C8 0xFFFFFFFF 0x80b880b8>;
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};
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prod_c_DDR133 {
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/* Prod values for DDR mode at 133MHz */
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};
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prod_c_DDR100 {
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/* Prod values for DDR mode at 100MHz */
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};
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prod_c_SDR133 {
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/* Prod values for SDR mode at 133MHz */
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};
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prod_c_SDR100 {
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/* Prod values for SDR mode at 100MHz */
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};
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};
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};
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