27 lines
689 B
Plaintext
27 lines
689 B
Plaintext
Allwinner SoCs High Speed Timer Controller
|
|
|
|
Required properties:
|
|
|
|
- compatible : should be "allwinner,sun5i-a13-hstimer" or
|
|
"allwinner,sun7i-a20-hstimer"
|
|
- reg : Specifies base physical address and size of the registers.
|
|
- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
|
|
one)
|
|
- clocks: phandle to the source clock (usually the AHB clock)
|
|
|
|
Optional properties:
|
|
- resets: phandle to a reset controller asserting the timer
|
|
|
|
Example:
|
|
|
|
timer@01c60000 {
|
|
compatible = "allwinner,sun7i-a20-hstimer";
|
|
reg = <0x01c60000 0x1000>;
|
|
interrupts = <0 51 1>,
|
|
<0 52 1>,
|
|
<0 53 1>,
|
|
<0 54 1>;
|
|
clocks = <&ahb1_gates 19>;
|
|
resets = <&ahb1rst 19>;
|
|
};
|