289 lines
7.2 KiB
C
289 lines
7.2 KiB
C
/*
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* arch/arm/plat-orion/pcie.c
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*
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* Marvell Orion SoC PCIe handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/mbus.h>
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#include <asm/mach/pci.h>
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#include <plat/pcie.h>
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#include <plat/addr-map.h>
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#include <linux/delay.h>
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/*
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* PCIe unit register offsets.
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*/
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#define PCIE_DEV_ID_OFF 0x0000
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#define PCIE_CMD_OFF 0x0004
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#define PCIE_DEV_REV_OFF 0x0008
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#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
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#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
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#define PCIE_HEADER_LOG_4_OFF 0x0128
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#define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
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#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
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#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
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#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
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#define PCIE_WIN5_CTRL_OFF 0x1880
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#define PCIE_WIN5_BASE_OFF 0x1884
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#define PCIE_WIN5_REMAP_OFF 0x188c
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#define PCIE_CONF_ADDR_OFF 0x18f8
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#define PCIE_CONF_ADDR_EN 0x80000000
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#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
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#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
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#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
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#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_MASK_OFF 0x1910
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_STAT_OFF 0x1a04
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#define PCIE_STAT_DEV_OFFS 20
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#define PCIE_STAT_DEV_MASK 0x1f
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#define PCIE_STAT_BUS_OFFS 8
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#define PCIE_STAT_BUS_MASK 0xff
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#define PCIE_STAT_LINK_DOWN 1
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET (1<<20)
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u32 orion_pcie_dev_id(void __iomem *base)
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{
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return readl(base + PCIE_DEV_ID_OFF) >> 16;
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}
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u32 orion_pcie_rev(void __iomem *base)
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{
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return readl(base + PCIE_DEV_REV_OFF) & 0xff;
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}
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int orion_pcie_link_up(void __iomem *base)
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{
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return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
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}
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int __init orion_pcie_x4_mode(void __iomem *base)
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{
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return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
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}
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int orion_pcie_get_local_bus_nr(void __iomem *base)
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{
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u32 stat = readl(base + PCIE_STAT_OFF);
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return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
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}
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void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
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{
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u32 stat;
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stat = readl(base + PCIE_STAT_OFF);
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stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
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stat |= nr << PCIE_STAT_BUS_OFFS;
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writel(stat, base + PCIE_STAT_OFF);
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}
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void __init orion_pcie_reset(void __iomem *base)
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{
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u32 reg;
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int i;
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/*
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* MV-S104860-U0, Rev. C:
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* PCI Express Unit Soft Reset
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* When set, generates an internal reset in the PCI Express unit.
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* This bit should be cleared after the link is re-established.
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*/
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reg = readl(base + PCIE_DEBUG_CTRL);
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reg |= PCIE_DEBUG_SOFT_RESET;
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writel(reg, base + PCIE_DEBUG_CTRL);
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for (i = 0; i < 20; i++) {
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mdelay(10);
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if (orion_pcie_link_up(base))
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break;
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}
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reg &= ~(PCIE_DEBUG_SOFT_RESET);
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writel(reg, base + PCIE_DEBUG_CTRL);
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}
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/*
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* Setup PCIE BARs and Address Decode Wins:
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* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
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* WIN[0-3] -> DRAM bank[0-3]
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*/
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static void __init orion_pcie_setup_wins(void __iomem *base)
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{
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const struct mbus_dram_target_info *dram;
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u32 size;
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int i;
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dram = mv_mbus_dram_info();
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/*
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* First, disable and clear BARs and windows.
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*/
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for (i = 1; i <= 2; i++) {
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writel(0, base + PCIE_BAR_CTRL_OFF(i));
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writel(0, base + PCIE_BAR_LO_OFF(i));
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writel(0, base + PCIE_BAR_HI_OFF(i));
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}
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for (i = 0; i < 5; i++) {
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writel(0, base + PCIE_WIN04_CTRL_OFF(i));
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writel(0, base + PCIE_WIN04_BASE_OFF(i));
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writel(0, base + PCIE_WIN04_REMAP_OFF(i));
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}
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writel(0, base + PCIE_WIN5_CTRL_OFF);
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writel(0, base + PCIE_WIN5_BASE_OFF);
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writel(0, base + PCIE_WIN5_REMAP_OFF);
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/*
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* Setup windows for DDR banks. Count total DDR size on the fly.
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*/
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size = 0;
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
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writel(0, base + PCIE_WIN04_REMAP_OFF(i));
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writel(((cs->size - 1) & 0xffff0000) |
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(cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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base + PCIE_WIN04_CTRL_OFF(i));
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size += cs->size;
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}
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/*
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* Round up 'size' to the nearest power of two.
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*/
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if ((size & (size - 1)) != 0)
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size = 1 << fls(size);
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/*
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* Setup BAR[1] to all DRAM banks.
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*/
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writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
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writel(0, base + PCIE_BAR_HI_OFF(1));
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writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
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}
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void __init orion_pcie_setup(void __iomem *base)
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{
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u16 cmd;
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u32 mask;
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/*
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* Point PCIe unit MBUS decode windows to DRAM space.
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*/
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orion_pcie_setup_wins(base);
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/*
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* Master + slave enable.
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*/
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cmd = readw(base + PCIE_CMD_OFF);
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cmd |= PCI_COMMAND_IO;
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cmd |= PCI_COMMAND_MEMORY;
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cmd |= PCI_COMMAND_MASTER;
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writew(cmd, base + PCIE_CMD_OFF);
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/*
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* Enable interrupt lines A-D.
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*/
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mask = readl(base + PCIE_MASK_OFF);
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mask |= 0x0f000000;
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writel(mask, base + PCIE_MASK_OFF);
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}
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int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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{
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writel(PCIE_CONF_BUS(bus->number) |
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PCIE_CONF_DEV(PCI_SLOT(devfn)) |
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PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
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PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
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base + PCIE_CONF_ADDR_OFF);
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*val = readl(base + PCIE_CONF_DATA_OFF);
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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return PCIBIOS_SUCCESSFUL;
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}
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int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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{
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writel(PCIE_CONF_BUS(bus->number) |
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PCIE_CONF_DEV(PCI_SLOT(devfn)) |
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PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
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PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
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base + PCIE_CONF_ADDR_OFF);
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*val = readl(base + PCIE_CONF_DATA_OFF);
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if (bus->number != orion_pcie_get_local_bus_nr(base) ||
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PCI_FUNC(devfn) != 0)
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*val = readl(base + PCIE_HEADER_LOG_4_OFF);
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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return PCIBIOS_SUCCESSFUL;
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}
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int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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{
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*val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
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PCIE_CONF_DEV(PCI_SLOT(devfn)) |
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PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
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PCIE_CONF_REG(where)));
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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return PCIBIOS_SUCCESSFUL;
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}
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int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 val)
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{
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int ret = PCIBIOS_SUCCESSFUL;
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writel(PCIE_CONF_BUS(bus->number) |
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PCIE_CONF_DEV(PCI_SLOT(devfn)) |
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PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
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PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
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base + PCIE_CONF_ADDR_OFF);
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if (size == 4) {
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writel(val, base + PCIE_CONF_DATA_OFF);
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} else if (size == 2) {
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writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
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} else if (size == 1) {
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writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
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} else {
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ret = PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return ret;
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}
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