642 lines
15 KiB
Plaintext
642 lines
15 KiB
Plaintext
/*
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* Devices shared by all Juno boards
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*/
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memtimer: timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <50000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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frame@2a830000 {
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frame-number = <1>;
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interrupts = <0 60 4>;
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reg = <0x0 0x2a830000 0x0 0x10000>;
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};
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};
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mailbox: mhu@2b1f0000 {
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compatible = "arm,mhu", "arm,primecell";
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reg = <0x0 0x2b1f0000 0x0 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mhu_lpri_rx",
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"mhu_hpri_rx";
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#mbox-cells = <1>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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reg = <0x0 0x2c010000 0 0x1000>,
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<0x0 0x2c02f000 0 0x2000>,
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<0x0 0x2c04f000 0 0x2000>,
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<0x0 0x2c06f000 0 0x2000>;
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
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ranges = <0 0 0 0x2c1c0000 0 0x40000>;
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v2m_0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0 0 0 0x1000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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};
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/*
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* Juno TRMs specify the size for these coresight components as 64K.
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* The actual size is just 4K though 64K is reserved. Access to the
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* unmapped reserved region results in a DECERR response.
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*/
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etf@20010000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0x20010000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* input port */
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port@0 {
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reg = <0>;
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etf_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&main_funnel_out_port>;
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};
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};
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/* output port */
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port@1 {
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reg = <0>;
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etf_out_port: endpoint {
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remote-endpoint = <&replicator_in_port0>;
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};
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};
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};
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};
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tpiu@20030000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0 0x20030000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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port {
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tpiu_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out_port0>;
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};
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};
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};
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main-funnel@20040000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0x20040000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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main_funnel_out_port: endpoint {
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remote-endpoint = <&etf_in_port>;
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};
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};
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port@1 {
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reg = <0>;
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main_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&cluster0_funnel_out_port>;
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};
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};
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port@2 {
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reg = <1>;
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main_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_funnel_out_port>;
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};
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};
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};
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};
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etr@20070000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0x20070000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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port {
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etr_in_port: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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etm0: etm@22040000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x22040000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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port {
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cluster0_etm0_out_port: endpoint {
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remote-endpoint = <&cluster0_funnel_in_port0>;
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};
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};
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};
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cluster0-funnel@220c0000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0x220c0000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster0_funnel_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port0>;
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};
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};
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port@1 {
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reg = <0>;
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cluster0_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&cluster0_etm0_out_port>;
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};
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};
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port@2 {
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reg = <1>;
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cluster0_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&cluster0_etm1_out_port>;
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};
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};
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};
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};
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etm1: etm@22140000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x22140000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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port {
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cluster0_etm1_out_port: endpoint {
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remote-endpoint = <&cluster0_funnel_in_port1>;
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};
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};
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};
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etm2: etm@23040000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x23040000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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port {
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cluster1_etm0_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port0>;
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};
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};
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};
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cluster1-funnel@230c0000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0x230c0000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster1_funnel_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port1>;
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};
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};
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port@1 {
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reg = <0>;
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cluster1_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_etm0_out_port>;
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};
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};
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port@2 {
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reg = <1>;
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cluster1_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_etm1_out_port>;
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};
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};
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port@3 {
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reg = <2>;
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cluster1_funnel_in_port2: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_etm2_out_port>;
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};
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};
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port@4 {
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reg = <3>;
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cluster1_funnel_in_port3: endpoint {
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slave-mode;
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remote-endpoint = <&cluster1_etm3_out_port>;
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};
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};
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};
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};
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etm3: etm@23140000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x23140000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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port {
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cluster1_etm1_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port1>;
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};
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};
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};
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etm4: etm@23240000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x23240000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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port {
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cluster1_etm2_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port2>;
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};
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};
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};
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etm5: etm@23340000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x23340000 0 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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power-domains = <&scpi_devpd 0>;
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port {
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cluster1_etm3_out_port: endpoint {
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remote-endpoint = <&cluster1_funnel_in_port3>;
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};
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};
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};
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coresight-replicator {
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/*
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* Non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-replicator";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&etr_in_port>;
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};
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};
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/* replicator input port */
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port@2 {
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reg = <0>;
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replicator_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etf_out_port>;
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};
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};
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};
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};
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sram: sram@2e000000 {
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compatible = "arm,juno-sram-ns", "mmio-sram";
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reg = <0x0 0x2e000000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x2e000000 0x8000>;
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cpu_scp_lpri: scp-shmem@0 {
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compatible = "arm,juno-scp-shmem";
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reg = <0x0 0x200>;
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};
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cpu_scp_hpri: scp-shmem@200 {
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compatible = "arm,juno-scp-shmem";
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reg = <0x200 0x200>;
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};
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};
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pcie_ctlr: pcie-controller@40000000 {
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compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
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device_type = "pci";
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reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
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bus-range = <0 255>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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dma-coherent;
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ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
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<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
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<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
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<0 0 0 2 &gic 0 0 0 137 4>,
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<0 0 0 3 &gic 0 0 0 138 4>,
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<0 0 0 4 &gic 0 0 0 139 4>;
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msi-parent = <&v2m_0>;
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status = "disabled";
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};
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scpi {
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compatible = "arm,scpi";
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mboxes = <&mailbox 1>;
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shmem = <&cpu_scp_hpri>;
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clocks {
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compatible = "arm,scpi-clocks";
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scpi_dvfs: scpi-dvfs {
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compatible = "arm,scpi-dvfs-clocks";
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#clock-cells = <1>;
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clock-indices = <0>, <1>, <2>;
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clock-output-names = "atlclk", "aplclk","gpuclk";
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};
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scpi_clk: scpi-clk {
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compatible = "arm,scpi-variable-clocks";
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#clock-cells = <1>;
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clock-indices = <3>;
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clock-output-names = "pxlclk";
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};
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};
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scpi_devpd: scpi-power-domains {
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compatible = "arm,scpi-power-domains";
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num-domains = <2>;
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#power-domain-cells = <1>;
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};
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scpi_sensors0: sensors {
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compatible = "arm,scpi-sensors";
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#thermal-sensor-cells = <1>;
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};
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};
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thermal-zones {
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pmic {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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thermal-sensors = <&scpi_sensors0 0>;
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};
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soc {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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thermal-sensors = <&scpi_sensors0 3>;
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};
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big_cluster_thermal_zone: big_cluster {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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thermal-sensors = <&scpi_sensors0 21>;
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status = "disabled";
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};
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little_cluster_thermal_zone: little_cluster {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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thermal-sensors = <&scpi_sensors0 22>;
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status = "disabled";
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};
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gpu0_thermal_zone: gpu0 {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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thermal-sensors = <&scpi_sensors0 23>;
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status = "disabled";
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};
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gpu1_thermal_zone: gpu1 {
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polling-delay = <1000>;
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polling-delay-passive = <100>;
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thermal-sensors = <&scpi_sensors0 24>;
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status = "disabled";
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};
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};
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/include/ "juno-clocks.dtsi"
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dma@7ff00000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0x7ff00000 0 0x1000>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_faxiclk>;
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clock-names = "apb_pclk";
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};
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hdlcd@7ff50000 {
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compatible = "arm,hdlcd";
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reg = <0 0x7ff50000 0 0x1000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scpi_clk 3>;
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clock-names = "pxlclk";
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port {
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hdlcd1_output: hdlcd1-endpoint {
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remote-endpoint = <&tda998x_1_input>;
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};
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};
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};
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hdlcd@7ff60000 {
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compatible = "arm,hdlcd";
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reg = <0 0x7ff60000 0 0x1000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scpi_clk 3>;
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clock-names = "pxlclk";
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port {
|
|
hdlcd0_output: hdlcd0-endpoint {
|
|
remote-endpoint = <&tda998x_0_input>;
|
|
};
|
|
};
|
|
};
|
|
|
|
soc_uart0: uart@7ff80000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x0 0x7ff80000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
};
|
|
|
|
i2c@7ffa0000 {
|
|
compatible = "snps,designware-i2c";
|
|
reg = <0x0 0x7ffa0000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <400000>;
|
|
i2c-sda-hold-time-ns = <500>;
|
|
clocks = <&soc_smc50mhz>;
|
|
|
|
hdmi-transmitter@70 {
|
|
compatible = "nxp,tda998x";
|
|
reg = <0x70>;
|
|
port {
|
|
tda998x_0_input: tda998x-0-endpoint {
|
|
remote-endpoint = <&hdlcd0_output>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi-transmitter@71 {
|
|
compatible = "nxp,tda998x";
|
|
reg = <0x71>;
|
|
port {
|
|
tda998x_1_input: tda998x-1-endpoint {
|
|
remote-endpoint = <&hdlcd1_output>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ohci@7ffb0000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0x0 0x7ffb0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&soc_usb48mhz>;
|
|
};
|
|
|
|
ehci@7ffc0000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x0 0x7ffc0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&soc_usb48mhz>;
|
|
};
|
|
|
|
memory-controller@7ffd0000 {
|
|
compatible = "arm,pl354", "arm,primecell";
|
|
reg = <0 0x7ffd0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&soc_smc50mhz>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
/* last 16MB of the first memory area is reserved for secure world use by firmware */
|
|
reg = <0x00000000 0x80000000 0x0 0x7f000000>,
|
|
<0x00000008 0x80000000 0x1 0x80000000>;
|
|
};
|
|
|
|
smb@08000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0x08000000 0x04000000>,
|
|
<1 0 0 0x14000000 0x04000000>,
|
|
<2 0 0 0x18000000 0x04000000>,
|
|
<3 0 0 0x1c000000 0x04000000>,
|
|
<4 0 0 0x0c000000 0x04000000>,
|
|
<5 0 0 0x10000000 0x04000000>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 15>;
|
|
interrupt-map = <0 0 0 &gic 0 0 0 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 1 &gic 0 0 0 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 2 &gic 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 3 &gic 0 0 0 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 4 &gic 0 0 0 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 5 &gic 0 0 0 162 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 6 &gic 0 0 0 163 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 7 &gic 0 0 0 164 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 8 &gic 0 0 0 165 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 9 &gic 0 0 0 166 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
/include/ "juno-motherboard.dtsi"
|
|
};
|
|
|
|
site2: tlx@60000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0x60000000 0x10000000>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0>;
|
|
interrupt-map = <0 0 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|