291 lines
13 KiB
C
291 lines
13 KiB
C
/*
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* DO NOT EDIT THIS FILE
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* This file is under version control at
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* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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* and can be replaced with that version at any time
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* DO NOT EDIT THIS FILE
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*
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* Copyright 2004-2011 Analog Devices Inc.
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* Licensed under the Clear BSD license.
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*/
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/* This file should be up to date with:
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* - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support old silicon - sorry */
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#if __SILICON_REVISION__ < 0
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# error will not work on BF526/BF527 silicon version
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#endif
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#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
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# define ANOMALY_BF526 1
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#else
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# define ANOMALY_BF526 0
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#endif
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#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
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# define ANOMALY_BF527 1
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#else
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# define ANOMALY_BF527 0
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#endif
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#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
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#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
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#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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#define ANOMALY_05000254 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
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#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
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/* Host DMA Boot Modes Are Not Functional */
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#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
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/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
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#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
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/* USB Calibration Value Is Not Initialized */
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#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* USB Calibration Value to use */
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#define ANOMALY_05000346_value 0xE510
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/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
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#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
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/* Security Features Are Not Functional */
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#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
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/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
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#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
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/* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Incorrect Default CSEL Value in PLL_DIV */
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#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
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#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
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/* Authentication Fails To Initiate */
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#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
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/* Data Read From L3 Memory by USB DMA May be Corrupted */
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#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
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/* 8-Bit NAND Flash Boot Mode Not Functional */
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#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Boot from OTP Memory Not Functional */
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#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
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/* bfrom_SysControl() Firmware Routine Not Functional */
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#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
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/* Programmable Preboot Settings Not Functional */
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#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
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/* CRC32 Checksum Support Not Functional */
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#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Reset Vector Must Not Be in SDRAM Memory Space */
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#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
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/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
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/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
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#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
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/* Log Buffer Not Functional */
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#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
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/* Hook Routine Not Functional */
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#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
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/* Header Indirect Bit Not Functional */
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#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
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/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
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#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
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/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
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#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
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/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
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#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
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/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
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#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
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#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Lockbox SESR Disallows Certain User Interrupts */
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#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
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#define ANOMALY_05000405 (1)
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/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
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#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
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#define ANOMALY_05000408 (1)
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/* Lockbox firmware leaves MDMA0 channel enabled */
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#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Incorrect Default Internal Voltage Regulator Setting */
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#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
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/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
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#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
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/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
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#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* DEB2_URGENT Bit Not Functional */
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#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
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#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
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/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
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#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
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#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
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#define ANOMALY_05000421 (1)
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/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
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#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
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/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
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#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Internal Voltage Regulator Not Trimmed */
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#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
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/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
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#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
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#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* Software System Reset Corrupts PLL_LOCKCNT Register */
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#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
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/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
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#define ANOMALY_05000431 (1)
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/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
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#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
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/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
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#define ANOMALY_05000434 (1)
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/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
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#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* Preboot Cannot be Used to Alter the PLL_DIV Register */
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#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
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#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* OTP Write Accesses Not Supported */
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#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* The WURESET Bit in the SYSCR Register is not Functional */
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#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
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/* USB DMA Short Packet Data Corruption */
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#define ANOMALY_05000450 (1)
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/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
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#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
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/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
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#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
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#define ANOMALY_05000456 (1)
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/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
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#define ANOMALY_05000457 (1)
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/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
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#define ANOMALY_05000460 (1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* USB Rx DMA Hang */
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#define ANOMALY_05000465 (1)
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/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
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#define ANOMALY_05000466 (1)
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/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
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#define ANOMALY_05000467 (1)
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000469 (1)
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/* Incorrect Default MSEL Value in PLL_CTL */
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#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition when Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
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#define ANOMALY_05000483 (1)
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/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
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#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
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/* The CODEC Zero-Cross Detect Feature is not Functional */
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#define ANOMALY_05000487 (1)
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/* SPI Master Boot Can Fail Under Certain Conditions */
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#define ANOMALY_05000490 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
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#define ANOMALY_05000498 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000149 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000171 (0)
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#define ANOMALY_05000179 (0)
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#define ANOMALY_05000182 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000189 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000219 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000233 (0)
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#define ANOMALY_05000234 (0)
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#define ANOMALY_05000242 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000248 (0)
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#define ANOMALY_05000250 (0)
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#define ANOMALY_05000257 (0)
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#define ANOMALY_05000261 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000274 (0)
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#define ANOMALY_05000278 (0)
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#define ANOMALY_05000281 (0)
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#define ANOMALY_05000283 (0)
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#define ANOMALY_05000285 (0)
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#define ANOMALY_05000287 (0)
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#define ANOMALY_05000301 (0)
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#define ANOMALY_05000305 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000312 (0)
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#define ANOMALY_05000315 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000362 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000383 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000402 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000480 (0)
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#define ANOMALY_16000030 (0)
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#endif
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