321 lines
5.6 KiB
ArmAsm
321 lines
5.6 KiB
ArmAsm
/*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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#include <mach/irq.h>
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#include <asm/dpmc.h>
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.section .l1.text
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ENTRY(_sleep_mode)
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[--SP] = (R7:4, P5:3);
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[--SP] = RETS;
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R1 = W[P0](z);
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BITSET (R1, 3);
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W[P0] = R1.L;
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CLI R2;
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SSYNC;
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IDLE;
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STI R2;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R7 = w[p0](z);
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BITCLR (R7, 3);
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BITCLR (R7, 5);
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w[p0] = R7.L;
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IDLE;
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bfin_init_pm_bench_cycles;
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call _test_pll_locked;
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RETS = [SP++];
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(R7:4, P5:3) = [SP++];
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RTS;
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ENDPROC(_sleep_mode)
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/*
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* This func never returns as it puts the part into hibernate, and
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* is only called from do_hibernate, so we don't bother saving or
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* restoring any of the normal C runtime state. When we wake up,
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* the entry point will be in do_hibernate and not here.
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*
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* We accept just one argument -- the value to write to VR_CTL.
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*/
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ENTRY(_hibernate_mode)
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/* Save/setup the regs we need early for minor pipeline optimization */
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R4 = R0;
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P3.H = hi(VR_CTL);
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P3.L = lo(VR_CTL);
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/* Disable all wakeup sources */
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R0 = IWR_DISABLE_ALL;
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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call _set_dram_srfs;
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SSYNC;
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/* Finally, we climb into our cave to hibernate */
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W[P3] = R4.L;
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bfin_init_pm_bench_cycles;
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CLI R2;
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IDLE;
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.Lforever:
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jump .Lforever;
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ENDPROC(_hibernate_mode)
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ENTRY(_sleep_deeper)
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[--SP] = (R7:4, P5:3);
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[--SP] = RETS;
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CLI R4;
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P3 = R0;
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P4 = R1;
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P5 = R2;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr;
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call _set_dram_srfs; /* Set SDRAM Self Refresh */
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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R6 = W[P0](z);
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R0.L = 0xF;
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W[P0] = R0.l; /* Set Max VCO to SCLK divider */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R5 = W[P0](z);
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R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
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W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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R7 = W[P0](z);
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R1 = 0x6;
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R1 <<= 16;
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R2 = 0x0404(Z);
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R1 = R1|R2;
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R2 = DEPOSIT(R7, R1);
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W[P0] = R2; /* Set Min Core Voltage */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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R0 = P3;
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R1 = P4;
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R3 = P5;
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call _set_sic_iwr; /* Set Awake from IDLE */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = W[P0](z);
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BITSET (R0, 3);
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W[P0] = R0.L; /* Turn CCLK OFF */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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R1 = IWR_DISABLE_ALL;
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R2 = IWR_DISABLE_ALL;
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call _set_sic_iwr; /* Set Awake from IDLE PLL */
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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W[P0]= R7;
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SSYNC;
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IDLE;
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bfin_init_pm_bench_cycles;
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call _test_pll_locked;
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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W[P0]= R6; /* Restore CCLK and SCLK divider */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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w[p0] = R5; /* Restore VCO multiplier */
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IDLE;
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call _test_pll_locked;
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call _unset_dram_srfs; /* SDRAM Self Refresh Off */
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STI R4;
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RETS = [SP++];
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(R7:4, P5:3) = [SP++];
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RTS;
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ENDPROC(_sleep_deeper)
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ENTRY(_set_dram_srfs)
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/* set the dram to self refresh mode */
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SSYNC;
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#if defined(EBIU_RSTCTL) /* DDR */
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P0.H = hi(EBIU_RSTCTL);
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P0.L = lo(EBIU_RSTCTL);
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R2 = [P0];
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BITSET(R2, 3); /* SRREQ enter self-refresh mode */
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[P0] = R2;
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SSYNC;
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1:
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R2 = [P0];
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CC = BITTST(R2, 4);
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if !CC JUMP 1b;
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#else /* SDRAM */
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P0.L = lo(EBIU_SDGCTL);
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P0.H = hi(EBIU_SDGCTL);
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P1.L = lo(EBIU_SDSTAT);
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P1.H = hi(EBIU_SDSTAT);
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R2 = [P0];
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BITSET(R2, 24); /* SRFS enter self-refresh mode */
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[P0] = R2;
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SSYNC;
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1:
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R2 = w[P1];
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SSYNC;
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cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
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if !cc jump 1b;
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R2 = [P0];
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BITCLR(R2, 0); /* SCTLE disable CLKOUT */
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[P0] = R2;
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#endif
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RTS;
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ENDPROC(_set_dram_srfs)
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ENTRY(_unset_dram_srfs)
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/* set the dram out of self refresh mode */
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#if defined(EBIU_RSTCTL) /* DDR */
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P0.H = hi(EBIU_RSTCTL);
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P0.L = lo(EBIU_RSTCTL);
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R2 = [P0];
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BITCLR(R2, 3); /* clear SRREQ bit */
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[P0] = R2;
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#elif defined(EBIU_SDGCTL) /* SDRAM */
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/* release CLKOUT from self-refresh */
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P0.L = lo(EBIU_SDGCTL);
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P0.H = hi(EBIU_SDGCTL);
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R2 = [P0];
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BITSET(R2, 0); /* SCTLE enable CLKOUT */
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[P0] = R2
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SSYNC;
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/* release SDRAM from self-refresh */
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R2 = [P0];
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BITCLR(R2, 24); /* clear SRFS bit */
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[P0] = R2
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#endif
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SSYNC;
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RTS;
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ENDPROC(_unset_dram_srfs)
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ENTRY(_set_sic_iwr)
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#ifdef SIC_IWR0
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P0.H = hi(SYSMMR_BASE);
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P0.L = lo(SYSMMR_BASE);
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[P0 + (SIC_IWR0 - SYSMMR_BASE)] = R0;
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[P0 + (SIC_IWR1 - SYSMMR_BASE)] = R1;
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# ifdef SIC_IWR2
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[P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
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# endif
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#else
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P0.H = hi(SIC_IWR);
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P0.L = lo(SIC_IWR);
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[P0] = R0;
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#endif
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SSYNC;
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RTS;
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ENDPROC(_set_sic_iwr)
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ENTRY(_test_pll_locked)
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P0.H = hi(PLL_STAT);
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P0.L = lo(PLL_STAT);
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1:
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R0 = W[P0] (Z);
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CC = BITTST(R0,5);
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IF !CC JUMP 1b;
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RTS;
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ENDPROC(_test_pll_locked)
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.section .text
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ENTRY(_do_hibernate)
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bfin_cpu_reg_save;
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bfin_sys_mmr_save;
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bfin_core_mmr_save;
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/* Setup args to hibernate mode early for pipeline optimization */
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R0 = M3;
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P1.H = _hibernate_mode;
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P1.L = _hibernate_mode;
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/* Save Magic, return address and Stack Pointer */
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P0 = 0;
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R1.H = 0xDEAD; /* Hibernate Magic */
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R1.L = 0xBEEF;
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R2.H = .Lpm_resume_here;
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R2.L = .Lpm_resume_here;
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[P0++] = R1; /* Store Hibernate Magic */
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[P0++] = R2; /* Save Return Address */
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[P0++] = SP; /* Save Stack Pointer */
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/* Must use an indirect call as we need to jump to L1 */
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call (P1); /* Goodbye */
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.Lpm_resume_here:
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bfin_core_mmr_restore;
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bfin_sys_mmr_restore;
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bfin_cpu_reg_restore;
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[--sp] = RETI; /* Clear Global Interrupt Disable */
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SP += 4;
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RTS;
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ENDPROC(_do_hibernate)
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