857 lines
22 KiB
C
857 lines
22 KiB
C
/*
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* Etrax general port I/O device
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*
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* Copyright (c) 1999-2007 Axis Communications AB
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*
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* Authors: Bjorn Wesen (initial version)
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* Ola Knutsson (LED handling)
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* Johan Adolfsson (read/set directions, write, port G)
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/fs.h>
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#include <linux/string.h>
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#include <linux/poll.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/etraxgpio.h>
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#include <arch/svinto.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <arch/io_interface_mux.h>
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#define GPIO_MAJOR 120 /* experimental MAJOR number */
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#define D(x)
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#if 0
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static int dp_cnt;
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#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
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#else
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#define DP(x)
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#endif
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static char gpio_name[] = "etrax gpio";
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#if 0
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static wait_queue_head_t *gpio_wq;
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#endif
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static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
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static ssize_t gpio_write(struct file *file, const char __user *buf,
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size_t count, loff_t *off);
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static int gpio_open(struct inode *inode, struct file *filp);
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static int gpio_release(struct inode *inode, struct file *filp);
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static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
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/* private data per open() of this driver */
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struct gpio_private {
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struct gpio_private *next;
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/* These fields are for PA and PB only */
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volatile unsigned char *port, *shadow;
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volatile unsigned char *dir, *dir_shadow;
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unsigned char changeable_dir;
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unsigned char changeable_bits;
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unsigned char clk_mask;
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unsigned char data_mask;
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unsigned char write_msb;
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unsigned char pad1, pad2, pad3;
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/* These fields are generic */
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unsigned long highalarm, lowalarm;
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wait_queue_head_t alarm_wq;
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int minor;
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};
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/* linked list of alarms to check for */
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static struct gpio_private *alarmlist;
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static int gpio_some_alarms; /* Set if someone uses alarm */
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static unsigned long gpio_pa_irq_enabled_mask;
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static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
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/* Port A and B use 8 bit access, but Port G is 32 bit */
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#define NUM_PORTS (GPIO_MINOR_B+1)
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static volatile unsigned char *ports[NUM_PORTS] = {
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R_PORT_PA_DATA,
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R_PORT_PB_DATA,
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};
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static volatile unsigned char *shads[NUM_PORTS] = {
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&port_pa_data_shadow,
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&port_pb_data_shadow
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};
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/* What direction bits that are user changeable 1=changeable*/
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#ifndef CONFIG_ETRAX_PA_CHANGEABLE_DIR
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#define CONFIG_ETRAX_PA_CHANGEABLE_DIR 0x00
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#endif
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#ifndef CONFIG_ETRAX_PB_CHANGEABLE_DIR
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#define CONFIG_ETRAX_PB_CHANGEABLE_DIR 0x00
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#endif
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#ifndef CONFIG_ETRAX_PA_CHANGEABLE_BITS
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#define CONFIG_ETRAX_PA_CHANGEABLE_BITS 0xFF
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#endif
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#ifndef CONFIG_ETRAX_PB_CHANGEABLE_BITS
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#define CONFIG_ETRAX_PB_CHANGEABLE_BITS 0xFF
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#endif
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static unsigned char changeable_dir[NUM_PORTS] = {
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CONFIG_ETRAX_PA_CHANGEABLE_DIR,
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CONFIG_ETRAX_PB_CHANGEABLE_DIR
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};
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static unsigned char changeable_bits[NUM_PORTS] = {
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CONFIG_ETRAX_PA_CHANGEABLE_BITS,
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CONFIG_ETRAX_PB_CHANGEABLE_BITS
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};
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static volatile unsigned char *dir[NUM_PORTS] = {
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R_PORT_PA_DIR,
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R_PORT_PB_DIR
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};
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static volatile unsigned char *dir_shadow[NUM_PORTS] = {
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&port_pa_dir_shadow,
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&port_pb_dir_shadow
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};
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/* All bits in port g that can change dir. */
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static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
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/* Port G is 32 bit, handle it special, some bits are both inputs
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and outputs at the same time, only some of the bits can change direction
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and some of them in groups of 8 bit. */
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static unsigned long changeable_dir_g;
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static unsigned long dir_g_in_bits;
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static unsigned long dir_g_out_bits;
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static unsigned long dir_g_shadow; /* 1=output */
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#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
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static unsigned int gpio_poll(struct file *file, poll_table *wait)
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{
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unsigned int mask = 0;
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struct gpio_private *priv = file->private_data;
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unsigned long data;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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poll_wait(file, &priv->alarm_wq, wait);
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if (priv->minor == GPIO_MINOR_A) {
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unsigned long tmp;
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data = *R_PORT_PA_DATA;
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/* PA has support for high level interrupt -
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* lets activate for those low and with highalarm set
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*/
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tmp = ~data & priv->highalarm & 0xFF;
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tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
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gpio_pa_irq_enabled_mask |= tmp;
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*R_IRQ_MASK1_SET = tmp;
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} else if (priv->minor == GPIO_MINOR_B)
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data = *R_PORT_PB_DATA;
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else if (priv->minor == GPIO_MINOR_G)
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data = *R_PORT_G_DATA;
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else {
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mask = 0;
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goto out;
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}
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if ((data & priv->highalarm) ||
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(~data & priv->lowalarm)) {
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mask = POLLIN|POLLRDNORM;
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}
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out:
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spin_unlock_irqrestore(&gpio_lock, flags);
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DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
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return mask;
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}
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int etrax_gpio_wake_up_check(void)
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{
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struct gpio_private *priv;
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unsigned long data = 0;
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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priv = alarmlist;
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while (priv) {
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if (USE_PORTS(priv))
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data = *priv->port;
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else if (priv->minor == GPIO_MINOR_G)
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data = *R_PORT_G_DATA;
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if ((data & priv->highalarm) ||
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(~data & priv->lowalarm)) {
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DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
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wake_up_interruptible(&priv->alarm_wq);
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ret = 1;
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}
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priv = priv->next;
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}
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spin_unlock_irqrestore(&gpio_lock, flags);
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return ret;
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}
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static irqreturn_t
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gpio_poll_timer_interrupt(int irq, void *dev_id)
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{
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if (gpio_some_alarms) {
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etrax_gpio_wake_up_check();
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static irqreturn_t
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gpio_interrupt(int irq, void *dev_id)
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{
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unsigned long tmp;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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/* Find what PA interrupts are active */
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tmp = (*R_IRQ_READ1);
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/* Find those that we have enabled */
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tmp &= gpio_pa_irq_enabled_mask;
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/* Clear them.. */
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*R_IRQ_MASK1_CLR = tmp;
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gpio_pa_irq_enabled_mask &= ~tmp;
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spin_unlock_irqrestore(&gpio_lock, flags);
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if (gpio_some_alarms)
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return IRQ_RETVAL(etrax_gpio_wake_up_check());
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return IRQ_NONE;
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}
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static void gpio_write_bit(struct gpio_private *priv,
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unsigned char data, int bit)
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{
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*priv->port = *priv->shadow &= ~(priv->clk_mask);
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if (data & 1 << bit)
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*priv->port = *priv->shadow |= priv->data_mask;
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else
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*priv->port = *priv->shadow &= ~(priv->data_mask);
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/* For FPGA: min 5.0ns (DCC) before CCLK high */
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*priv->port = *priv->shadow |= priv->clk_mask;
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}
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static void gpio_write_byte(struct gpio_private *priv, unsigned char data)
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{
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int i;
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if (priv->write_msb)
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for (i = 7; i >= 0; i--)
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gpio_write_bit(priv, data, i);
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else
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for (i = 0; i <= 7; i++)
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gpio_write_bit(priv, data, i);
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}
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static ssize_t gpio_write(struct file *file, const char __user *buf,
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size_t count, loff_t *off)
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{
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struct gpio_private *priv = file->private_data;
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unsigned long flags;
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ssize_t retval = count;
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if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B)
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return -EFAULT;
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if (!access_ok(VERIFY_READ, buf, count))
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return -EFAULT;
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spin_lock_irqsave(&gpio_lock, flags);
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/* It must have been configured using the IO_CFG_WRITE_MODE */
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/* Perhaps a better error code? */
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if (priv->clk_mask == 0 || priv->data_mask == 0) {
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retval = -EPERM;
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goto out;
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}
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D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X "
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"clk 0x%02X msb: %i\n",
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count, priv->data_mask, priv->clk_mask, priv->write_msb));
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while (count--)
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gpio_write_byte(priv, *buf++);
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out:
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spin_unlock_irqrestore(&gpio_lock, flags);
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return retval;
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}
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static int
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gpio_open(struct inode *inode, struct file *filp)
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{
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struct gpio_private *priv;
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int p = iminor(inode);
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unsigned long flags;
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if (p > GPIO_MINOR_LAST)
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return -EINVAL;
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priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->minor = p;
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/* initialize the io/alarm struct */
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if (USE_PORTS(priv)) { /* A and B */
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priv->port = ports[p];
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priv->shadow = shads[p];
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priv->dir = dir[p];
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priv->dir_shadow = dir_shadow[p];
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priv->changeable_dir = changeable_dir[p];
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priv->changeable_bits = changeable_bits[p];
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} else {
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priv->port = NULL;
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priv->shadow = NULL;
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priv->dir = NULL;
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priv->dir_shadow = NULL;
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priv->changeable_dir = 0;
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priv->changeable_bits = 0;
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}
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priv->highalarm = 0;
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priv->lowalarm = 0;
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priv->clk_mask = 0;
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priv->data_mask = 0;
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init_waitqueue_head(&priv->alarm_wq);
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filp->private_data = priv;
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/* link it into our alarmlist */
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spin_lock_irqsave(&gpio_lock, flags);
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priv->next = alarmlist;
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alarmlist = priv;
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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static int
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gpio_release(struct inode *inode, struct file *filp)
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{
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struct gpio_private *p;
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struct gpio_private *todel;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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p = alarmlist;
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todel = filp->private_data;
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/* unlink from alarmlist and free the private structure */
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if (p == todel) {
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alarmlist = todel->next;
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} else {
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while (p->next != todel)
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p = p->next;
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p->next = todel->next;
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}
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kfree(todel);
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/* Check if there are still any alarms set */
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p = alarmlist;
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while (p) {
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if (p->highalarm | p->lowalarm) {
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gpio_some_alarms = 1;
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goto out;
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}
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p = p->next;
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}
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gpio_some_alarms = 0;
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out:
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spin_unlock_irqrestore(&gpio_lock, flags);
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return 0;
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}
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/* Main device API. ioctl's to read/set/clear bits, as well as to
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* set alarms to wait for using a subsequent select().
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*/
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unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
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{
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/* Set direction 0=unchanged 1=input,
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* return mask with 1=input */
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if (USE_PORTS(priv)) {
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*priv->dir = *priv->dir_shadow &=
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~((unsigned char)arg & priv->changeable_dir);
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return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
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}
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if (priv->minor != GPIO_MINOR_G)
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return 0;
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/* We must fiddle with R_GEN_CONFIG to change dir */
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if (((arg & dir_g_in_bits) != arg) &&
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(arg & changeable_dir_g)) {
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arg &= changeable_dir_g;
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/* Clear bits in genconfig to set to input */
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if (arg & (1<<0)) {
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genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir);
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dir_g_in_bits |= (1<<0);
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dir_g_out_bits &= ~(1<<0);
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}
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if ((arg & 0x0000FF00) == 0x0000FF00) {
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genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir);
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dir_g_in_bits |= 0x0000FF00;
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dir_g_out_bits &= ~0x0000FF00;
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}
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if ((arg & 0x00FF0000) == 0x00FF0000) {
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genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir);
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dir_g_in_bits |= 0x00FF0000;
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dir_g_out_bits &= ~0x00FF0000;
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}
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if (arg & (1<<24)) {
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genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir);
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dir_g_in_bits |= (1<<24);
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dir_g_out_bits &= ~(1<<24);
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}
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D(printk(KERN_DEBUG "gpio: SETINPUT on port G set "
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"genconfig to 0x%08lX "
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"in_bits: 0x%08lX "
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"out_bits: 0x%08lX\n",
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(unsigned long)genconfig_shadow,
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dir_g_in_bits, dir_g_out_bits));
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*R_GEN_CONFIG = genconfig_shadow;
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/* Must be a >120 ns delay before writing this again */
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}
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return dir_g_in_bits;
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} /* setget_input */
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unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
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{
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if (USE_PORTS(priv)) {
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*priv->dir = *priv->dir_shadow |=
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((unsigned char)arg & priv->changeable_dir);
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return *priv->dir_shadow;
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}
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if (priv->minor != GPIO_MINOR_G)
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return 0;
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/* We must fiddle with R_GEN_CONFIG to change dir */
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if (((arg & dir_g_out_bits) != arg) &&
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(arg & changeable_dir_g)) {
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/* Set bits in genconfig to set to output */
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if (arg & (1<<0)) {
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genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir);
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dir_g_out_bits |= (1<<0);
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dir_g_in_bits &= ~(1<<0);
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}
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if ((arg & 0x0000FF00) == 0x0000FF00) {
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genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir);
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dir_g_out_bits |= 0x0000FF00;
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dir_g_in_bits &= ~0x0000FF00;
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}
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if ((arg & 0x00FF0000) == 0x00FF0000) {
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genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir);
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dir_g_out_bits |= 0x00FF0000;
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dir_g_in_bits &= ~0x00FF0000;
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}
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if (arg & (1<<24)) {
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genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir);
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dir_g_out_bits |= (1<<24);
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dir_g_in_bits &= ~(1<<24);
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}
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D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
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"genconfig to 0x%08lX "
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"in_bits: 0x%08lX "
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"out_bits: 0x%08lX\n",
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(unsigned long)genconfig_shadow,
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dir_g_in_bits, dir_g_out_bits));
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*R_GEN_CONFIG = genconfig_shadow;
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/* Must be a >120 ns delay before writing this again */
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}
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return dir_g_out_bits & 0x7FFFFFFF;
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} /* setget_output */
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static int
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gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
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static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
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{
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unsigned long flags;
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unsigned long val;
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int ret = 0;
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struct gpio_private *priv = file->private_data;
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if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
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return -EINVAL;
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switch (_IOC_NR(cmd)) {
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case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
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// read the port
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spin_lock_irqsave(&gpio_lock, flags);
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if (USE_PORTS(priv)) {
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ret = *priv->port;
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} else if (priv->minor == GPIO_MINOR_G) {
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|
ret = (*R_PORT_G_DATA) & 0x7FFFFFFF;
|
|
}
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
|
|
break;
|
|
case IO_SETBITS:
|
|
// set changeable bits with a 1 in arg
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
|
|
if (USE_PORTS(priv)) {
|
|
*priv->port = *priv->shadow |=
|
|
((unsigned char)arg & priv->changeable_bits);
|
|
} else if (priv->minor == GPIO_MINOR_G) {
|
|
*R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
|
|
}
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
|
|
break;
|
|
case IO_CLRBITS:
|
|
// clear changeable bits with a 1 in arg
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
if (USE_PORTS(priv)) {
|
|
*priv->port = *priv->shadow &=
|
|
~((unsigned char)arg & priv->changeable_bits);
|
|
} else if (priv->minor == GPIO_MINOR_G) {
|
|
*R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
|
|
}
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_HIGHALARM:
|
|
// set alarm when bits with 1 in arg go high
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
priv->highalarm |= arg;
|
|
gpio_some_alarms = 1;
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_LOWALARM:
|
|
// set alarm when bits with 1 in arg go low
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
priv->lowalarm |= arg;
|
|
gpio_some_alarms = 1;
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_CLRALARM:
|
|
/* clear alarm for bits with 1 in arg */
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
priv->highalarm &= ~arg;
|
|
priv->lowalarm &= ~arg;
|
|
{
|
|
/* Must update gpio_some_alarms */
|
|
struct gpio_private *p = alarmlist;
|
|
int some_alarms;
|
|
p = alarmlist;
|
|
some_alarms = 0;
|
|
while (p) {
|
|
if (p->highalarm | p->lowalarm) {
|
|
some_alarms = 1;
|
|
break;
|
|
}
|
|
p = p->next;
|
|
}
|
|
gpio_some_alarms = some_alarms;
|
|
}
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
|
|
/* Read direction 0=input 1=output */
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
if (USE_PORTS(priv)) {
|
|
ret = *priv->dir_shadow;
|
|
} else if (priv->minor == GPIO_MINOR_G) {
|
|
/* Note: Some bits are both in and out,
|
|
* Those that are dual is set here as well.
|
|
*/
|
|
ret = (dir_g_shadow | dir_g_out_bits) & 0x7FFFFFFF;
|
|
}
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
|
|
/* Set direction 0=unchanged 1=input,
|
|
* return mask with 1=input
|
|
*/
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
ret = setget_input(priv, arg) & 0x7FFFFFFF;
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
|
|
/* Set direction 0=unchanged 1=output,
|
|
* return mask with 1=output
|
|
*/
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
ret = setget_output(priv, arg) & 0x7FFFFFFF;
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_SHUTDOWN:
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
SOFT_SHUTDOWN();
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_GET_PWR_BT:
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
#if defined (CONFIG_ETRAX_SOFT_SHUTDOWN)
|
|
ret = (*R_PORT_G_DATA & ( 1 << CONFIG_ETRAX_POWERBUTTON_BIT));
|
|
#else
|
|
ret = 0;
|
|
#endif
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_CFG_WRITE_MODE:
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
priv->clk_mask = arg & 0xFF;
|
|
priv->data_mask = (arg >> 8) & 0xFF;
|
|
priv->write_msb = (arg >> 16) & 0x01;
|
|
/* Check if we're allowed to change the bits and
|
|
* the direction is correct
|
|
*/
|
|
if (!((priv->clk_mask & priv->changeable_bits) &&
|
|
(priv->data_mask & priv->changeable_bits) &&
|
|
(priv->clk_mask & *priv->dir_shadow) &&
|
|
(priv->data_mask & *priv->dir_shadow)))
|
|
{
|
|
priv->clk_mask = 0;
|
|
priv->data_mask = 0;
|
|
ret = -EPERM;
|
|
}
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
break;
|
|
case IO_READ_INBITS:
|
|
/* *arg is result of reading the input pins */
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
if (USE_PORTS(priv)) {
|
|
val = *priv->port;
|
|
} else if (priv->minor == GPIO_MINOR_G) {
|
|
val = *R_PORT_G_DATA;
|
|
}
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
|
ret = -EFAULT;
|
|
break;
|
|
case IO_READ_OUTBITS:
|
|
/* *arg is result of reading the output shadow */
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
if (USE_PORTS(priv)) {
|
|
val = *priv->shadow;
|
|
} else if (priv->minor == GPIO_MINOR_G) {
|
|
val = port_g_data_shadow;
|
|
}
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
|
ret = -EFAULT;
|
|
break;
|
|
case IO_SETGET_INPUT:
|
|
/* bits set in *arg is set to input,
|
|
* *arg updated with current input pins.
|
|
*/
|
|
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
|
|
{
|
|
ret = -EFAULT;
|
|
break;
|
|
}
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
val = setget_input(priv, val);
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
|
ret = -EFAULT;
|
|
break;
|
|
case IO_SETGET_OUTPUT:
|
|
/* bits set in *arg is set to output,
|
|
* *arg updated with current output pins.
|
|
*/
|
|
if (copy_from_user(&val, (void __user *)arg, sizeof(val))) {
|
|
ret = -EFAULT;
|
|
break;
|
|
}
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
val = setget_output(priv, val);
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
|
|
ret = -EFAULT;
|
|
break;
|
|
default:
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
if (priv->minor == GPIO_MINOR_LEDS)
|
|
ret = gpio_leds_ioctl(cmd, arg);
|
|
else
|
|
ret = -EINVAL;
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
} /* switch */
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
|
|
{
|
|
unsigned char green;
|
|
unsigned char red;
|
|
|
|
switch (_IOC_NR(cmd)) {
|
|
case IO_LEDACTIVE_SET:
|
|
green = ((unsigned char)arg) & 1;
|
|
red = (((unsigned char)arg) >> 1) & 1;
|
|
CRIS_LED_ACTIVE_SET_G(green);
|
|
CRIS_LED_ACTIVE_SET_R(red);
|
|
break;
|
|
|
|
case IO_LED_SETBIT:
|
|
CRIS_LED_BIT_SET(arg);
|
|
break;
|
|
|
|
case IO_LED_CLRBIT:
|
|
CRIS_LED_BIT_CLR(arg);
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
} /* switch */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct file_operations gpio_fops = {
|
|
.owner = THIS_MODULE,
|
|
.poll = gpio_poll,
|
|
.unlocked_ioctl = gpio_ioctl,
|
|
.write = gpio_write,
|
|
.open = gpio_open,
|
|
.release = gpio_release,
|
|
.llseek = noop_llseek,
|
|
};
|
|
|
|
static void ioif_watcher(const unsigned int gpio_in_available,
|
|
const unsigned int gpio_out_available,
|
|
const unsigned char pa_available,
|
|
const unsigned char pb_available)
|
|
{
|
|
unsigned long int flags;
|
|
|
|
D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n"));
|
|
D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x "
|
|
"PA: 0x%02x PB: 0x%02x\n",
|
|
gpio_in_available, gpio_out_available,
|
|
pa_available, pb_available));
|
|
|
|
spin_lock_irqsave(&gpio_lock, flags);
|
|
|
|
dir_g_in_bits = gpio_in_available;
|
|
dir_g_out_bits = gpio_out_available;
|
|
|
|
/* Initialise the dir_g_shadow etc. depending on genconfig */
|
|
/* 0=input 1=output */
|
|
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
|
|
dir_g_shadow |= (1 << 0);
|
|
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
|
|
dir_g_shadow |= 0x0000FF00;
|
|
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out))
|
|
dir_g_shadow |= 0x00FF0000;
|
|
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out))
|
|
dir_g_shadow |= (1 << 24);
|
|
|
|
changeable_dir_g = changeable_dir_g_mask;
|
|
changeable_dir_g &= dir_g_out_bits;
|
|
changeable_dir_g &= dir_g_in_bits;
|
|
|
|
/* Correct the bits that can change direction */
|
|
dir_g_out_bits &= ~changeable_dir_g;
|
|
dir_g_out_bits |= dir_g_shadow;
|
|
dir_g_in_bits &= ~changeable_dir_g;
|
|
dir_g_in_bits |= (~dir_g_shadow & changeable_dir_g);
|
|
|
|
spin_unlock_irqrestore(&gpio_lock, flags);
|
|
|
|
printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX "
|
|
"val: %08lX\n",
|
|
dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
|
|
printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
|
|
dir_g_shadow, changeable_dir_g);
|
|
}
|
|
|
|
/* main driver initialization routine, called from mem.c */
|
|
|
|
static int __init gpio_init(void)
|
|
{
|
|
int res;
|
|
#if defined (CONFIG_ETRAX_CSP0_LEDS)
|
|
int i;
|
|
#endif
|
|
|
|
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
|
|
if (res < 0) {
|
|
printk(KERN_ERR "gpio: couldn't get a major number.\n");
|
|
return res;
|
|
}
|
|
|
|
/* Clear all leds */
|
|
#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
|
|
CRIS_LED_NETWORK_SET(0);
|
|
CRIS_LED_ACTIVE_SET(0);
|
|
CRIS_LED_DISK_READ(0);
|
|
CRIS_LED_DISK_WRITE(0);
|
|
|
|
#if defined (CONFIG_ETRAX_CSP0_LEDS)
|
|
for (i = 0; i < 32; i++)
|
|
CRIS_LED_BIT_SET(i);
|
|
#endif
|
|
|
|
#endif
|
|
/* The I/O interface allocation watcher will be called when
|
|
* registering it. */
|
|
if (cris_io_interface_register_watcher(ioif_watcher)){
|
|
printk(KERN_WARNING "gpio_init: Failed to install IO "
|
|
"if allocator watcher\n");
|
|
}
|
|
|
|
printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 "
|
|
"Axis Communications AB\n");
|
|
/* We call etrax_gpio_wake_up_check() from timer interrupt and
|
|
* from default_idle() in kernel/process.c
|
|
* The check in default_idle() reduces latency from ~15 ms to ~6 ms
|
|
* in some tests.
|
|
*/
|
|
res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
|
|
IRQF_SHARED, "gpio poll", gpio_name);
|
|
if (res) {
|
|
printk(KERN_CRIT "err: timer0 irq for gpio\n");
|
|
return res;
|
|
}
|
|
res = request_irq(PA_IRQ_NBR, gpio_interrupt,
|
|
IRQF_SHARED, "gpio PA", gpio_name);
|
|
if (res)
|
|
printk(KERN_CRIT "err: PA irq for gpio\n");
|
|
|
|
return res;
|
|
}
|
|
|
|
/* this makes sure that gpio_init is called during kernel boot */
|
|
module_init(gpio_init);
|
|
|