172 lines
4.1 KiB
C
172 lines
4.1 KiB
C
/*
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* arch/cris/arch-v32/drivers/nandflash.c
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*
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* Copyright (c) 2004
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*
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* Derived from drivers/mtd/nand/spia.c
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* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <arch/memmap.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/gio_defs.h>
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#include <hwregs/bif_core_defs.h>
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#include <asm/io.h>
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#define CE_BIT 4
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#define CLE_BIT 5
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#define ALE_BIT 6
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#define BY_BIT 7
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struct mtd_info_wrapper {
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struct nand_chip chip;
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};
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/* Bitmask for control pins */
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#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
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/* Bitmask for mtd nand control bits */
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#define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)
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static struct mtd_info *crisv32_mtd;
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/*
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* hardware specific access to control-lines
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*/
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static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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unsigned long flags;
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reg_gio_rw_pa_dout dout;
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struct nand_chip *this = mtd_to_nand(mtd);
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local_irq_save(flags);
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/* control bits change */
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if (ctrl & NAND_CTRL_CHANGE) {
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dout = REG_RD(gio, regi_gio, rw_pa_dout);
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dout.data &= ~PIN_BITMASK;
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#if (CE_BIT == 4 && NAND_NCE == 1 && \
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CLE_BIT == 5 && NAND_CLE == 2 && \
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ALE_BIT == 6 && NAND_ALE == 4)
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/* Pins in same order as control bits, but shifted.
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* Optimize for this case; works for 2.6.18 */
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dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT;
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#else
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/* the slow way */
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if (!(ctrl & NAND_NCE))
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dout.data |= (1 << CE_BIT);
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if (ctrl & NAND_CLE)
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dout.data |= (1 << CLE_BIT);
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if (ctrl & NAND_ALE)
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dout.data |= (1 << ALE_BIT);
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#endif
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REG_WR(gio, regi_gio, rw_pa_dout, dout);
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}
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/* command to chip */
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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local_irq_restore(flags);
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}
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/*
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* read device ready pin
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*/
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static int crisv32_device_ready(struct mtd_info *mtd)
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{
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reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
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return ((din.data & (1 << BY_BIT)) >> BY_BIT);
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}
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/*
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* Main initialization routine
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*/
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struct mtd_info *__init crisv32_nand_flash_probe(void)
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{
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void __iomem *read_cs;
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void __iomem *write_cs;
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reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core,
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rw_grp3_cfg);
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reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
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struct mtd_info_wrapper *wrapper;
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struct nand_chip *this;
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int err = 0;
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/* Allocate memory for MTD device structure and private data */
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wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
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if (!wrapper) {
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printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
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"device structure.\n");
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err = -ENOMEM;
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return NULL;
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}
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read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
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write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
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if (!read_cs || !write_cs) {
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printk(KERN_ERR "CRISv32 NAND ioremap failed\n");
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err = -EIO;
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goto out_mtd;
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}
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/* Get pointer to private data */
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this = &wrapper->chip;
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crisv32_mtd = nand_to_mtd(this);
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pa_oe.oe |= 1 << CE_BIT;
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pa_oe.oe |= 1 << ALE_BIT;
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pa_oe.oe |= 1 << CLE_BIT;
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pa_oe.oe &= ~(1 << BY_BIT);
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REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
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bif_cfg.gated_csp0 = regk_bif_core_rd;
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bif_cfg.gated_csp1 = regk_bif_core_wr;
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REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = read_cs;
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this->IO_ADDR_W = write_cs;
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this->cmd_ctrl = crisv32_hwcontrol;
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this->dev_ready = crisv32_device_ready;
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/* 20 us command delay time */
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this->chip_delay = 20;
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this->ecc.mode = NAND_ECC_SOFT;
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this->ecc.algo = NAND_ECC_HAMMING;
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/* Enable the following for a flash based bad block table */
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/* this->bbt_options = NAND_BBT_USE_FLASH; */
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/* Scan to find existence of the device */
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if (nand_scan(crisv32_mtd, 1)) {
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err = -ENXIO;
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goto out_ior;
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}
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return crisv32_mtd;
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out_ior:
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iounmap((void *)read_cs);
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iounmap((void *)write_cs);
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out_mtd:
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kfree(wrapper);
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return NULL;
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}
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