175 lines
4.6 KiB
C
175 lines
4.6 KiB
C
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#include <asm/spr-regs.h>
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#ifdef __ATOMIC_LIB__
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#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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#define ATOMIC_QUALS
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#define ATOMIC_EXPORT(x) EXPORT_SYMBOL(x)
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#else /* !OUTOFLINE && LIB */
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#define ATOMIC_OP_RETURN(op)
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#define ATOMIC_FETCH_OP(op)
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#endif /* OUTOFLINE */
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#else /* !__ATOMIC_LIB__ */
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#define ATOMIC_EXPORT(x)
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#ifdef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
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#define ATOMIC_OP_RETURN(op) \
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extern int __atomic_##op##_return(int i, int *v); \
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extern long long __atomic64_##op##_return(long long i, long long *v);
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#define ATOMIC_FETCH_OP(op) \
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extern int __atomic32_fetch_##op(int i, int *v); \
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extern long long __atomic64_fetch_##op(long long i, long long *v);
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#else /* !OUTOFLINE && !LIB */
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#define ATOMIC_QUALS static inline
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#endif /* OUTOFLINE */
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#endif /* __ATOMIC_LIB__ */
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/*
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* Note on the 64 bit inline asm variants...
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*
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* CSTD is a conditional instruction and needs a constrained memory reference.
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* Normally 'U' provides the correct constraints for conditional instructions
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* and this is used for the 32 bit version, however 'U' does not appear to work
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* for 64 bit values (gcc-4.9)
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*
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* The exact constraint is that conditional instructions cannot deal with an
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* immediate displacement in the memory reference, so what we do is we read the
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* address through a volatile cast into a local variable in order to insure we
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* _have_ to compute the correct address without displacement. This allows us
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* to use the regular 'm' for the memory address.
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*
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* Furthermore, the %Ln operand, which prints the low word register (r+1),
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* really only works for registers, this means we cannot allow immediate values
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* for the 64 bit versions -- like we do for the 32 bit ones.
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*
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*/
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#ifndef ATOMIC_OP_RETURN
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#define ATOMIC_OP_RETURN(op) \
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ATOMIC_QUALS int __atomic_##op##_return(int i, int *v) \
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{ \
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int val; \
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\
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asm volatile( \
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"0: \n" \
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" orcc gr0,gr0,gr0,icc3 \n" \
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" ckeq icc3,cc7 \n" \
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" ld.p %M0,%1 \n" \
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" orcr cc7,cc7,cc3 \n" \
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" "#op"%I2 %1,%2,%1 \n" \
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" cst.p %1,%M0 ,cc3,#1 \n" \
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
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" beq icc3,#0,0b \n" \
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: "+U"(*v), "=&r"(val) \
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: "NPr"(i) \
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: "memory", "cc7", "cc3", "icc3" \
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); \
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\
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return val; \
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} \
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ATOMIC_EXPORT(__atomic_##op##_return); \
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\
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ATOMIC_QUALS long long __atomic64_##op##_return(long long i, long long *v) \
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{ \
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long long *__v = READ_ONCE(v); \
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long long val; \
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\
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asm volatile( \
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"0: \n" \
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" orcc gr0,gr0,gr0,icc3 \n" \
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" ckeq icc3,cc7 \n" \
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" ldd.p %M0,%1 \n" \
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" orcr cc7,cc7,cc3 \n" \
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" "#op"cc %L1,%L2,%L1,icc0 \n" \
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" "#op"x %1,%2,%1,icc0 \n" \
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" cstd.p %1,%M0 ,cc3,#1 \n" \
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
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" beq icc3,#0,0b \n" \
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: "+m"(*__v), "=&e"(val) \
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: "e"(i) \
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: "memory", "cc7", "cc3", "icc0", "icc3" \
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); \
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\
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return val; \
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} \
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ATOMIC_EXPORT(__atomic64_##op##_return);
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#endif
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#ifndef ATOMIC_FETCH_OP
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#define ATOMIC_FETCH_OP(op) \
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ATOMIC_QUALS int __atomic32_fetch_##op(int i, int *v) \
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{ \
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int old, tmp; \
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\
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asm volatile( \
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"0: \n" \
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" orcc gr0,gr0,gr0,icc3 \n" \
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" ckeq icc3,cc7 \n" \
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" ld.p %M0,%1 \n" \
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" orcr cc7,cc7,cc3 \n" \
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" "#op"%I3 %1,%3,%2 \n" \
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" cst.p %2,%M0 ,cc3,#1 \n" \
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
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" beq icc3,#0,0b \n" \
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: "+U"(*v), "=&r"(old), "=r"(tmp) \
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: "NPr"(i) \
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: "memory", "cc7", "cc3", "icc3" \
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); \
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\
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return old; \
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} \
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ATOMIC_EXPORT(__atomic32_fetch_##op); \
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\
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ATOMIC_QUALS long long __atomic64_fetch_##op(long long i, long long *v) \
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{ \
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long long *__v = READ_ONCE(v); \
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long long old, tmp; \
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\
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asm volatile( \
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"0: \n" \
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" orcc gr0,gr0,gr0,icc3 \n" \
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" ckeq icc3,cc7 \n" \
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" ldd.p %M0,%1 \n" \
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" orcr cc7,cc7,cc3 \n" \
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" "#op" %L1,%L3,%L2 \n" \
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" "#op" %1,%3,%2 \n" \
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" cstd.p %2,%M0 ,cc3,#1 \n" \
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" corcc gr29,gr29,gr0 ,cc3,#1 \n" \
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" beq icc3,#0,0b \n" \
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: "+m"(*__v), "=&e"(old), "=e"(tmp) \
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: "e"(i) \
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: "memory", "cc7", "cc3", "icc3" \
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); \
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\
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return old; \
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} \
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ATOMIC_EXPORT(__atomic64_fetch_##op);
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#endif
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ATOMIC_FETCH_OP(or)
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ATOMIC_FETCH_OP(and)
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ATOMIC_FETCH_OP(xor)
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ATOMIC_FETCH_OP(add)
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ATOMIC_FETCH_OP(sub)
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ATOMIC_OP_RETURN(add)
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ATOMIC_OP_RETURN(sub)
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_QUALS
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#undef ATOMIC_EXPORT
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