185 lines
4.3 KiB
ArmAsm
185 lines
4.3 KiB
ArmAsm
/* tlb-flush.S: TLB flushing routines
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/spr-regs.h>
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.macro DEBUG ch
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# sethi.p %hi(0xfeff9c00),gr4
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# setlo %lo(0xfeff9c00),gr4
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# setlos #\ch,gr5
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# stbi gr5,@(gr4,#0)
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# membar
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.endm
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.section .rodata
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# sizes corresponding to TPXR.LMAX
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.balign 1
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__tlb_lmax_sizes:
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.byte 0, 64, 0, 0
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.byte 0, 0, 0, 0
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.byte 0, 0, 0, 0
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.byte 0, 0, 0, 0
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.section .text
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.balign 4
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###############################################################################
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#
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# flush everything
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# - void __flush_tlb_all(void)
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#
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###############################################################################
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.globl __flush_tlb_all
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.type __flush_tlb_all,@function
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__flush_tlb_all:
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DEBUG 'A'
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# kill cached PGE value
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setlos #0xffffffff,gr4
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movgs gr4,scr0
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movgs gr4,scr1
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# kill AMPR-cached TLB values
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movgs gr0,iamlr1
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movgs gr0,iampr1
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movgs gr0,damlr1
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movgs gr0,dampr1
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# find out how many lines there are
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movsg tpxr,gr5
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sethi.p %hi(__tlb_lmax_sizes),gr4
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srli gr5,#TPXR_LMAX_SHIFT,gr5
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setlo.p %lo(__tlb_lmax_sizes),gr4
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andi gr5,#TPXR_LMAX_SMASK,gr5
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ldub @(gr4,gr5),gr4
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# now, we assume that the TLB line step is page size in size
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setlos.p #PAGE_SIZE,gr5
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setlos #0,gr6
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1:
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tlbpr gr6,gr0,#6,#0
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subicc.p gr4,#1,gr4,icc0
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add gr6,gr5,gr6
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bne icc0,#2,1b
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DEBUG 'B'
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bralr
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.size __flush_tlb_all, .-__flush_tlb_all
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###############################################################################
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#
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# flush everything to do with one context
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# - void __flush_tlb_mm(unsigned long contextid [GR8])
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#
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###############################################################################
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.globl __flush_tlb_mm
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.type __flush_tlb_mm,@function
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__flush_tlb_mm:
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DEBUG 'M'
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# kill cached PGE value
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setlos #0xffffffff,gr4
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movgs gr4,scr0
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movgs gr4,scr1
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# specify the context we want to flush
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movgs gr8,tplr
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# find out how many lines there are
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movsg tpxr,gr5
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sethi.p %hi(__tlb_lmax_sizes),gr4
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srli gr5,#TPXR_LMAX_SHIFT,gr5
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setlo.p %lo(__tlb_lmax_sizes),gr4
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andi gr5,#TPXR_LMAX_SMASK,gr5
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ldub @(gr4,gr5),gr4
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# now, we assume that the TLB line step is page size in size
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setlos.p #PAGE_SIZE,gr5
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setlos #0,gr6
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0:
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tlbpr gr6,gr0,#5,#0
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subicc.p gr4,#1,gr4,icc0
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add gr6,gr5,gr6
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bne icc0,#2,0b
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DEBUG 'N'
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bralr
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.size __flush_tlb_mm, .-__flush_tlb_mm
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###############################################################################
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#
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# flush a range of addresses from the TLB
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# - void __flush_tlb_page(unsigned long contextid [GR8],
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# unsigned long start [GR9])
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#
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###############################################################################
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.globl __flush_tlb_page
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.type __flush_tlb_page,@function
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__flush_tlb_page:
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# kill cached PGE value
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setlos #0xffffffff,gr4
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movgs gr4,scr0
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movgs gr4,scr1
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# specify the context we want to flush
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movgs gr8,tplr
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# zap the matching TLB line and AMR values
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setlos #~(PAGE_SIZE-1),gr5
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and gr9,gr5,gr9
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tlbpr gr9,gr0,#5,#0
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bralr
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.size __flush_tlb_page, .-__flush_tlb_page
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###############################################################################
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#
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# flush a range of addresses from the TLB
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# - void __flush_tlb_range(unsigned long contextid [GR8],
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# unsigned long start [GR9],
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# unsigned long end [GR10])
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#
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###############################################################################
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.globl __flush_tlb_range
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.type __flush_tlb_range,@function
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__flush_tlb_range:
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# kill cached PGE value
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setlos #0xffffffff,gr4
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movgs gr4,scr0
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movgs gr4,scr1
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# specify the context we want to flush
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movgs gr8,tplr
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# round the start down to beginning of TLB line and end up to beginning of next TLB line
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setlos.p #~(PAGE_SIZE-1),gr5
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setlos #PAGE_SIZE,gr6
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subi.p gr10,#1,gr10
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and gr9,gr5,gr9
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and gr10,gr5,gr10
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2:
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tlbpr gr9,gr0,#5,#0
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subcc.p gr9,gr10,gr0,icc0
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add gr9,gr6,gr9
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bne icc0,#0,2b ; most likely a 1-page flush
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bralr
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.size __flush_tlb_range, .-__flush_tlb_range
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