299 lines
7.6 KiB
C
299 lines
7.6 KiB
C
/*
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* linux/arch/m68k/mm/memory.c
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*
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* Copyright (C) 1995 Hamish Macdonald
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/pagemap.h>
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#include <linux/gfp.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
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struct page instead of separately kmalloced struct. Stolen from
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arch/sparc/mm/srmmu.c ... */
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typedef struct list_head ptable_desc;
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static LIST_HEAD(ptable_list);
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#define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
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#define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
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#define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)
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#define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
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void __init init_pointer_table(unsigned long ptable)
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{
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ptable_desc *dp;
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unsigned long page = ptable & PAGE_MASK;
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unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);
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dp = PD_PTABLE(page);
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if (!(PD_MARKBITS(dp) & mask)) {
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PD_MARKBITS(dp) = 0xff;
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list_add(dp, &ptable_list);
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}
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PD_MARKBITS(dp) &= ~mask;
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#ifdef DEBUG
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printk("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
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#endif
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/* unreserve the page so it's possible to free that page */
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PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
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init_page_count(PD_PAGE(dp));
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return;
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}
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pmd_t *get_pointer_table (void)
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{
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ptable_desc *dp = ptable_list.next;
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unsigned char mask = PD_MARKBITS (dp);
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unsigned char tmp;
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unsigned int off;
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/*
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* For a pointer table for a user process address space, a
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* table is taken from a page allocated for the purpose. Each
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* page can hold 8 pointer tables. The page is remapped in
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* virtual address space to be noncacheable.
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*/
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if (mask == 0) {
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void *page;
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ptable_desc *new;
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if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
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return NULL;
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flush_tlb_kernel_page(page);
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nocache_page(page);
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new = PD_PTABLE(page);
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PD_MARKBITS(new) = 0xfe;
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list_add_tail(new, dp);
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return (pmd_t *)page;
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}
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for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
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;
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PD_MARKBITS(dp) = mask & ~tmp;
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if (!PD_MARKBITS(dp)) {
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/* move to end of list */
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list_move_tail(dp, &ptable_list);
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}
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return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
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}
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int free_pointer_table (pmd_t *ptable)
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{
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ptable_desc *dp;
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unsigned long page = (unsigned long)ptable & PAGE_MASK;
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unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);
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dp = PD_PTABLE(page);
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if (PD_MARKBITS (dp) & mask)
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panic ("table already free!");
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PD_MARKBITS (dp) |= mask;
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if (PD_MARKBITS(dp) == 0xff) {
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/* all tables in page are free, free page */
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list_del(dp);
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cache_page((void *)page);
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free_page (page);
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return 1;
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} else if (ptable_list.next != dp) {
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/*
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* move this descriptor to the front of the list, since
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* it has one or more free tables.
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*/
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list_move(dp, &ptable_list);
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}
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return 0;
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}
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/* invalidate page in both caches */
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static inline void clear040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cinvp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* invalidate page in i-cache */
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static inline void cleari040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cinvp %%ic,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* push page in both caches */
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/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
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static inline void push040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* push and invalidate page in both caches, must disable ints
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* to avoid invalidating valid data */
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static inline void pushcl040(unsigned long paddr)
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{
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unsigned long flags;
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local_irq_save(flags);
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push040(paddr);
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if (CPU_IS_060)
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clear040(paddr);
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local_irq_restore(flags);
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}
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/*
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* 040: Hit every page containing an address in the range paddr..paddr+len-1.
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* (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
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* Hit every page until there is a page or less to go. Hit the next page,
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* and the one after that if the range hits it.
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*/
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/* ++roman: A little bit more care is required here: The CINVP instruction
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* invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
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* and the end of the region must be treated differently if they are not
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* exactly at the beginning or end of a page boundary. Else, maybe too much
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* data becomes invalidated and thus lost forever. CPUSHP does what we need:
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* it invalidates the page after pushing dirty data to memory. (Thanks to Jes
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* for discovering the problem!)
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*/
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/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
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* the DPI bit in the CACR; would it cause problems with temporarily changing
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* this?). So we have to push first and then additionally to invalidate.
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*/
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/*
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* cache_clear() semantics: Clear any cache entries for the area in question,
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* without writing back dirty entries first. This is useful if the data will
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* be overwritten anyway, e.g. by DMA to memory. The range is defined by a
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* _physical_ address.
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*/
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void cache_clear (unsigned long paddr, int len)
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{
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if (CPU_IS_COLDFIRE) {
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clear_cf_bcache(0, DCACHE_MAX_ADDR);
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} else if (CPU_IS_040_OR_060) {
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int tmp;
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/*
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* We need special treatment for the first page, in case it
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* is not page-aligned. Page align the addresses to work
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* around bug I17 in the 68060.
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*/
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if ((tmp = -paddr & (PAGE_SIZE - 1))) {
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pushcl040(paddr & PAGE_MASK);
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if ((len -= tmp) <= 0)
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return;
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paddr += tmp;
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}
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tmp = PAGE_SIZE;
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paddr &= PAGE_MASK;
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while ((len -= tmp) >= 0) {
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clear040(paddr);
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paddr += tmp;
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}
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if ((len += tmp))
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/* a page boundary gets crossed at the end */
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pushcl040(paddr);
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}
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else /* 68030 or 68020 */
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asm volatile ("movec %/cacr,%/d0\n\t"
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"oriw %0,%/d0\n\t"
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"movec %/d0,%/cacr"
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: : "i" (FLUSH_I_AND_D)
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: "d0");
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#ifdef CONFIG_M68K_L2_CACHE
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if(mach_l2_flush)
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mach_l2_flush(0);
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#endif
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}
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EXPORT_SYMBOL(cache_clear);
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/*
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* cache_push() semantics: Write back any dirty cache data in the given area,
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* and invalidate the range in the instruction cache. It needs not (but may)
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* invalidate those entries also in the data cache. The range is defined by a
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* _physical_ address.
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*/
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void cache_push (unsigned long paddr, int len)
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{
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if (CPU_IS_COLDFIRE) {
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flush_cf_bcache(0, DCACHE_MAX_ADDR);
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} else if (CPU_IS_040_OR_060) {
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int tmp = PAGE_SIZE;
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/*
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* on 68040 or 68060, push cache lines for pages in the range;
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* on the '040 this also invalidates the pushed lines, but not on
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* the '060!
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*/
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len += paddr & (PAGE_SIZE - 1);
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/*
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* Work around bug I17 in the 68060 affecting some instruction
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* lines not being invalidated properly.
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*/
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paddr &= PAGE_MASK;
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do {
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push040(paddr);
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paddr += tmp;
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} while ((len -= tmp) > 0);
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}
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/*
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* 68030/68020 have no writeback cache. On the other hand,
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* cache_push is actually a superset of cache_clear (the lines
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* get written back and invalidated), so we should make sure
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* to perform the corresponding actions. After all, this is getting
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* called in places where we've just loaded code, or whatever, so
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* flushing the icache is appropriate; flushing the dcache shouldn't
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* be required.
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*/
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else /* 68030 or 68020 */
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asm volatile ("movec %/cacr,%/d0\n\t"
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"oriw %0,%/d0\n\t"
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"movec %/d0,%/cacr"
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: : "i" (FLUSH_I)
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: "d0");
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#ifdef CONFIG_M68K_L2_CACHE
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if(mach_l2_flush)
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mach_l2_flush(1);
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#endif
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}
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EXPORT_SYMBOL(cache_push);
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