59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008 Cavium Networks
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*/
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#ifndef __OCTEON_IRQ_H__
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#define __OCTEON_IRQ_H__
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#define NR_IRQS OCTEON_IRQ_LAST
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#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
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enum octeon_irq {
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/* 1 - 8 represent the 8 MIPS standard interrupt sources */
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OCTEON_IRQ_SW0 = 1,
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OCTEON_IRQ_SW1,
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/* CIU0, CUI2, CIU4 are 3, 4, 5 */
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OCTEON_IRQ_5 = 6,
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OCTEON_IRQ_PERF,
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OCTEON_IRQ_TIMER,
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/* sources in CIU_INTX_EN0 */
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OCTEON_IRQ_WORKQ0,
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OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
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OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
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OCTEON_IRQ_MBOX1,
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OCTEON_IRQ_MBOX2,
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OCTEON_IRQ_MBOX3,
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OCTEON_IRQ_PCI_INT0,
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OCTEON_IRQ_PCI_INT1,
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OCTEON_IRQ_PCI_INT2,
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OCTEON_IRQ_PCI_INT3,
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OCTEON_IRQ_PCI_MSI0,
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OCTEON_IRQ_PCI_MSI1,
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OCTEON_IRQ_PCI_MSI2,
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OCTEON_IRQ_PCI_MSI3,
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OCTEON_IRQ_TWSI,
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OCTEON_IRQ_TWSI2,
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OCTEON_IRQ_RML,
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OCTEON_IRQ_TIMER0,
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OCTEON_IRQ_TIMER1,
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OCTEON_IRQ_TIMER2,
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OCTEON_IRQ_TIMER3,
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#ifndef CONFIG_PCI_MSI
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OCTEON_IRQ_LAST = 127
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#endif
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};
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#ifdef CONFIG_PCI_MSI
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/* 256 - 511 represent the MSI interrupts 0-255 */
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#define OCTEON_IRQ_MSI_BIT0 (256)
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#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
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#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
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#endif
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#endif
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