388 lines
9.7 KiB
C
388 lines
9.7 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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* Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/pm.h>
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#include <linux/export.h>
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/reset-controller.h>
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#include <asm/reboot.h>
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#include <lantiq_soc.h>
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#include "../prom.h"
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/* reset request register */
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#define RCU_RST_REQ 0x0010
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/* reset status register */
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#define RCU_RST_STAT 0x0014
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/* vr9 gphy registers */
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#define RCU_GFS_ADD0_XRX200 0x0020
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#define RCU_GFS_ADD1_XRX200 0x0068
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/* xRX300 gphy registers */
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#define RCU_GFS_ADD0_XRX300 0x0020
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#define RCU_GFS_ADD1_XRX300 0x0058
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#define RCU_GFS_ADD2_XRX300 0x00AC
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/* xRX330 gphy registers */
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#define RCU_GFS_ADD0_XRX330 0x0020
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#define RCU_GFS_ADD1_XRX330 0x0058
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#define RCU_GFS_ADD2_XRX330 0x00AC
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#define RCU_GFS_ADD3_XRX330 0x0264
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/* xbar BE flag */
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#define RCU_AHB_ENDIAN 0x004C
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#define RCU_VR9_BE_AHB1S 0x00000008
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/* reboot bit */
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#define RCU_RD_GPHY0_XRX200 BIT(31)
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#define RCU_RD_SRST BIT(30)
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#define RCU_RD_GPHY1_XRX200 BIT(29)
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/* xRX300 bits */
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#define RCU_RD_GPHY0_XRX300 BIT(31)
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#define RCU_RD_GPHY1_XRX300 BIT(29)
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#define RCU_RD_GPHY2_XRX300 BIT(28)
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/* xRX330 bits */
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#define RCU_RD_GPHY0_XRX330 BIT(31)
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#define RCU_RD_GPHY1_XRX330 BIT(29)
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#define RCU_RD_GPHY2_XRX330 BIT(28)
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#define RCU_RD_GPHY3_XRX330 BIT(10)
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/* reset cause */
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#define RCU_STAT_SHIFT 26
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/* boot selection */
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#define RCU_BOOT_SEL(x) ((x >> 18) & 0x7)
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#define RCU_BOOT_SEL_XRX200(x) (((x >> 17) & 0xf) | ((x >> 8) & 0x10))
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/* dwc2 USB configuration registers */
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#define RCU_USB1CFG 0x0018
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#define RCU_USB2CFG 0x0034
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/* USB DMA endianness bits */
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#define RCU_USBCFG_HDSEL_BIT BIT(11)
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#define RCU_USBCFG_HOST_END_BIT BIT(10)
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#define RCU_USBCFG_SLV_END_BIT BIT(9)
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/* USB reset bits */
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#define RCU_USBRESET 0x0010
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#define USBRESET_BIT BIT(4)
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#define RCU_USBRESET2 0x0048
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#define USB1RESET_BIT BIT(4)
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#define USB2RESET_BIT BIT(5)
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#define RCU_CFG1A 0x0038
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#define RCU_CFG1B 0x003C
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/* USB PMU devices */
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#define PMU_AHBM BIT(15)
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#define PMU_USB0 BIT(6)
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#define PMU_USB1 BIT(27)
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/* USB PHY PMU devices */
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#define PMU_USB0_P BIT(0)
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#define PMU_USB1_P BIT(26)
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/* remapped base addr of the reset control unit */
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static void __iomem *ltq_rcu_membase;
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static struct device_node *ltq_rcu_np;
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static DEFINE_SPINLOCK(ltq_rcu_lock);
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static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
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{
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ltq_w32(val, ltq_rcu_membase + reg_off);
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}
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static uint32_t ltq_rcu_r32(uint32_t reg_off)
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{
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return ltq_r32(ltq_rcu_membase + reg_off);
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}
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static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
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{
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unsigned long flags;
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spin_lock_irqsave(<q_rcu_lock, flags);
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ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
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spin_unlock_irqrestore(<q_rcu_lock, flags);
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}
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/* This function is used by the watchdog driver */
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int ltq_reset_cause(void)
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{
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u32 val = ltq_rcu_r32(RCU_RST_STAT);
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return val >> RCU_STAT_SHIFT;
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}
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EXPORT_SYMBOL_GPL(ltq_reset_cause);
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/* allow platform code to find out what source we booted from */
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unsigned char ltq_boot_select(void)
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{
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u32 val = ltq_rcu_r32(RCU_RST_STAT);
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if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
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return RCU_BOOT_SEL_XRX200(val);
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return RCU_BOOT_SEL(val);
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}
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struct ltq_gphy_reset {
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u32 rd;
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u32 addr;
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};
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/* reset / boot a gphy */
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static struct ltq_gphy_reset xrx200_gphy[] = {
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{RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
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{RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
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};
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/* reset / boot a gphy */
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static struct ltq_gphy_reset xrx300_gphy[] = {
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{RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300},
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{RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300},
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{RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300},
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};
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/* reset / boot a gphy */
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static struct ltq_gphy_reset xrx330_gphy[] = {
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{RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330},
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{RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330},
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{RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330},
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{RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330},
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};
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static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs,
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dma_addr_t dev_addr)
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{
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ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ);
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ltq_rcu_w32(dev_addr, phy_regs->addr);
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ltq_rcu_w32_mask(phy_regs->rd, 0, RCU_RST_REQ);
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}
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/* reset and boot a gphy. these phys only exist on xrx200 SoC */
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int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
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{
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struct clk *clk;
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if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
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dev_err(dev, "this SoC has no GPHY\n");
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return -EINVAL;
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}
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if (of_machine_is_compatible("lantiq,vr9")) {
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clk = clk_get_sys("1f203000.rcu", "gphy");
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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clk_enable(clk);
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}
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dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
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if (of_machine_is_compatible("lantiq,vr9")) {
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if (id >= ARRAY_SIZE(xrx200_gphy)) {
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dev_err(dev, "%u is an invalid gphy id\n", id);
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return -EINVAL;
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}
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xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr);
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} else if (of_machine_is_compatible("lantiq,ar10")) {
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if (id >= ARRAY_SIZE(xrx300_gphy)) {
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dev_err(dev, "%u is an invalid gphy id\n", id);
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return -EINVAL;
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}
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xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr);
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} else if (of_machine_is_compatible("lantiq,grx390")) {
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if (id >= ARRAY_SIZE(xrx330_gphy)) {
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dev_err(dev, "%u is an invalid gphy id\n", id);
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return -EINVAL;
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}
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xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr);
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}
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return 0;
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}
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/* reset a io domain for u micro seconds */
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void ltq_reset_once(unsigned int module, ulong u)
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{
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ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
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udelay(u);
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ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
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}
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static int ltq_assert_device(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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u32 val;
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if (id < 8)
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return -1;
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val = ltq_rcu_r32(RCU_RST_REQ);
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val |= BIT(id);
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ltq_rcu_w32(val, RCU_RST_REQ);
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return 0;
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}
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static int ltq_deassert_device(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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u32 val;
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if (id < 8)
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return -1;
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val = ltq_rcu_r32(RCU_RST_REQ);
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val &= ~BIT(id);
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ltq_rcu_w32(val, RCU_RST_REQ);
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return 0;
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}
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static int ltq_reset_device(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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ltq_assert_device(rcdev, id);
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return ltq_deassert_device(rcdev, id);
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}
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static const struct reset_control_ops reset_ops = {
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.reset = ltq_reset_device,
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.assert = ltq_assert_device,
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.deassert = ltq_deassert_device,
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};
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static struct reset_controller_dev reset_dev = {
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.ops = &reset_ops,
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.owner = THIS_MODULE,
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.nr_resets = 32,
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.of_reset_n_cells = 1,
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};
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void ltq_rst_init(void)
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{
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reset_dev.of_node = of_find_compatible_node(NULL, NULL,
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"lantiq,xway-reset");
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if (!reset_dev.of_node)
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pr_err("Failed to find reset controller node");
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else
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reset_controller_register(&reset_dev);
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}
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static void ltq_machine_restart(char *command)
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{
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u32 val = ltq_rcu_r32(RCU_RST_REQ);
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if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
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val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
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val |= RCU_RD_SRST;
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local_irq_disable();
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ltq_rcu_w32(val, RCU_RST_REQ);
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unreachable();
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}
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static void ltq_machine_halt(void)
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{
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local_irq_disable();
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unreachable();
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}
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static void ltq_machine_power_off(void)
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{
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local_irq_disable();
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unreachable();
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}
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static void ltq_usb_init(void)
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{
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/* Power for USB cores 1 & 2 */
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ltq_pmu_enable(PMU_AHBM);
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ltq_pmu_enable(PMU_USB0);
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ltq_pmu_enable(PMU_USB1);
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ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
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ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
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/* Enable USB PHY power for cores 1 & 2 */
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ltq_pmu_enable(PMU_USB0_P);
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ltq_pmu_enable(PMU_USB1_P);
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/* Configure cores to host mode */
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ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
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RCU_USB1CFG);
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ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
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RCU_USB2CFG);
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/* Select DMA endianness (Host-endian: big-endian) */
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ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
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| RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
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ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
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| RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
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/* Hard reset USB state machines */
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ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
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udelay(50 * 1000);
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ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
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/* Soft reset USB state machines */
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ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
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| USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
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udelay(50 * 1000);
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ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
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& ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
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}
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static int __init mips_reboot_setup(void)
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{
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struct resource res;
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ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
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if (!ltq_rcu_np)
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ltq_rcu_np = of_find_compatible_node(NULL, NULL,
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"lantiq,rcu-xrx200");
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/* check if all the reset register range is available */
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if (!ltq_rcu_np)
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panic("Failed to load reset resources from devicetree");
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if (of_address_to_resource(ltq_rcu_np, 0, &res))
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panic("Failed to get rcu memory range");
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if (!request_mem_region(res.start, resource_size(&res), res.name))
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pr_err("Failed to request rcu memory");
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ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
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if (!ltq_rcu_membase)
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panic("Failed to remap core memory");
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if (of_machine_is_compatible("lantiq,ar9") ||
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of_machine_is_compatible("lantiq,vr9"))
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ltq_usb_init();
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if (of_machine_is_compatible("lantiq,vr9"))
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ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
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RCU_AHB_ENDIAN);
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_machine_restart = ltq_machine_restart;
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_machine_halt = ltq_machine_halt;
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pm_power_off = ltq_machine_power_off;
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return 0;
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}
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arch_initcall(mips_reboot_setup);
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