416 lines
10 KiB
C
416 lines
10 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*
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* Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
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* Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
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* Copyright 1999 Hewlett Packard Co.
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*
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*/
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#include <linux/mm.h>
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#include <linux/ptrace.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/extable.h>
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#include <linux/uaccess.h>
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#include <asm/traps.h>
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/* Various important other fields */
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#define bit22set(x) (x & 0x00000200)
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#define bits23_25set(x) (x & 0x000001c0)
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#define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
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/* extended opcode is 0x6a */
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#define BITSSET 0x1c0 /* for identifying LDCW */
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DEFINE_PER_CPU(struct exception_data, exception_data);
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int show_unhandled_signals = 1;
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/*
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* parisc_acctyp(unsigned int inst) --
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* Given a PA-RISC memory access instruction, determine if the
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* the instruction would perform a memory read or memory write
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* operation.
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*
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* This function assumes that the given instruction is a memory access
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* instruction (i.e. you should really only call it if you know that
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* the instruction has generated some sort of a memory access fault).
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*
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* Returns:
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* VM_READ if read operation
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* VM_WRITE if write operation
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* VM_EXEC if execute operation
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*/
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static unsigned long
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parisc_acctyp(unsigned long code, unsigned int inst)
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{
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if (code == 6 || code == 16)
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return VM_EXEC;
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switch (inst & 0xf0000000) {
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case 0x40000000: /* load */
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case 0x50000000: /* new load */
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return VM_READ;
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case 0x60000000: /* store */
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case 0x70000000: /* new store */
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return VM_WRITE;
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case 0x20000000: /* coproc */
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case 0x30000000: /* coproc2 */
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if (bit22set(inst))
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return VM_WRITE;
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case 0x0: /* indexed/memory management */
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if (bit22set(inst)) {
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/*
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* Check for the 'Graphics Flush Read' instruction.
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* It resembles an FDC instruction, except for bits
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* 20 and 21. Any combination other than zero will
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* utilize the block mover functionality on some
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* older PA-RISC platforms. The case where a block
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* move is performed from VM to graphics IO space
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* should be treated as a READ.
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*
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* The significance of bits 20,21 in the FDC
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* instruction is:
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*
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* 00 Flush data cache (normal instruction behavior)
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* 01 Graphics flush write (IO space -> VM)
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* 10 Graphics flush read (VM -> IO space)
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* 11 Graphics flush read/write (VM <-> IO space)
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*/
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if (isGraphicsFlushRead(inst))
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return VM_READ;
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return VM_WRITE;
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} else {
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/*
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* Check for LDCWX and LDCWS (semaphore instructions).
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* If bits 23 through 25 are all 1's it is one of
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* the above two instructions and is a write.
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*
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* Note: With the limited bits we are looking at,
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* this will also catch PROBEW and PROBEWI. However,
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* these should never get in here because they don't
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* generate exceptions of the type:
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* Data TLB miss fault/data page fault
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* Data memory protection trap
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*/
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if (bits23_25set(inst) == BITSSET)
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return VM_WRITE;
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}
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return VM_READ; /* Default */
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}
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return VM_READ; /* Default */
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}
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#undef bit22set
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#undef bits23_25set
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#undef isGraphicsFlushRead
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#undef BITSSET
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#if 0
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/* This is the treewalk to find a vma which is the highest that has
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* a start < addr. We're using find_vma_prev instead right now, but
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* we might want to use this at some point in the future. Probably
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* not, but I want it committed to CVS so I don't lose it :-)
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*/
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while (tree != vm_avl_empty) {
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if (tree->vm_start > addr) {
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tree = tree->vm_avl_left;
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} else {
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prev = tree;
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if (prev->vm_next == NULL)
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break;
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if (prev->vm_next->vm_start > addr)
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break;
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tree = tree->vm_avl_right;
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}
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}
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#endif
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int fixup_exception(struct pt_regs *regs)
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{
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const struct exception_table_entry *fix;
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fix = search_exception_tables(regs->iaoq[0]);
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if (fix) {
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struct exception_data *d;
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d = this_cpu_ptr(&exception_data);
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d->fault_ip = regs->iaoq[0];
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d->fault_gp = regs->gr[27];
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d->fault_space = regs->isr;
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d->fault_addr = regs->ior;
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/*
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* Fix up get_user() and put_user().
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* ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
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* bit in the relative address of the fixup routine to indicate
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* that %r8 should be loaded with -EFAULT to report a userspace
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* access error.
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*/
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if (fix->fixup & 1) {
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regs->gr[8] = -EFAULT;
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/* zero target register for get_user() */
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if (parisc_acctyp(0, regs->iir) == VM_READ) {
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int treg = regs->iir & 0x1f;
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regs->gr[treg] = 0;
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}
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}
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regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
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regs->iaoq[0] &= ~3;
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/*
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* NOTE: In some cases the faulting instruction
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* may be in the delay slot of a branch. We
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* don't want to take the branch, so we don't
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* increment iaoq[1], instead we set it to be
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* iaoq[0]+4, and clear the B bit in the PSW
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*/
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regs->iaoq[1] = regs->iaoq[0] + 4;
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regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
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return 1;
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}
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return 0;
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}
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/*
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* parisc hardware trap list
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*
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* Documented in section 3 "Addressing and Access Control" of the
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* "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
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* https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
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*
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* For implementation see handle_interruption() in traps.c
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*/
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static const char * const trap_description[] = {
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[1] "High-priority machine check (HPMC)",
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[2] "Power failure interrupt",
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[3] "Recovery counter trap",
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[5] "Low-priority machine check",
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[6] "Instruction TLB miss fault",
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[7] "Instruction access rights / protection trap",
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[8] "Illegal instruction trap",
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[9] "Break instruction trap",
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[10] "Privileged operation trap",
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[11] "Privileged register trap",
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[12] "Overflow trap",
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[13] "Conditional trap",
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[14] "FP Assist Exception trap",
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[15] "Data TLB miss fault",
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[16] "Non-access ITLB miss fault",
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[17] "Non-access DTLB miss fault",
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[18] "Data memory protection/unaligned access trap",
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[19] "Data memory break trap",
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[20] "TLB dirty bit trap",
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[21] "Page reference trap",
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[22] "Assist emulation trap",
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[25] "Taken branch trap",
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[26] "Data memory access rights trap",
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[27] "Data memory protection ID trap",
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[28] "Unaligned data reference trap",
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};
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const char *trap_name(unsigned long code)
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{
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const char *t = NULL;
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if (code < ARRAY_SIZE(trap_description))
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t = trap_description[code];
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return t ? t : "Unknown trap";
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}
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/*
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* Print out info about fatal segfaults, if the show_unhandled_signals
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* sysctl is set:
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*/
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static inline void
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show_signal_msg(struct pt_regs *regs, unsigned long code,
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unsigned long address, struct task_struct *tsk,
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struct vm_area_struct *vma)
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{
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if (!unhandled_signal(tsk, SIGSEGV))
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return;
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if (!printk_ratelimit())
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return;
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pr_warn("\n");
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pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
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tsk->comm, code, address);
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print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);
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pr_cont("\ntrap #%lu: %s%c", code, trap_name(code),
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vma ? ',':'\n');
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if (vma)
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pr_warn(KERN_CONT " vm_start = 0x%08lx, vm_end = 0x%08lx\n",
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vma->vm_start, vma->vm_end);
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show_regs(regs);
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}
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void do_page_fault(struct pt_regs *regs, unsigned long code,
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unsigned long address)
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{
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struct vm_area_struct *vma, *prev_vma;
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struct task_struct *tsk;
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struct mm_struct *mm;
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unsigned long acc_type;
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int fault;
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unsigned int flags;
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if (faulthandler_disabled())
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goto no_context;
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tsk = current;
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mm = tsk->mm;
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if (!mm)
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goto no_context;
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flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
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if (user_mode(regs))
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flags |= FAULT_FLAG_USER;
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acc_type = parisc_acctyp(code, regs->iir);
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if (acc_type & VM_WRITE)
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flags |= FAULT_FLAG_WRITE;
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retry:
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down_read(&mm->mmap_sem);
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vma = find_vma_prev(mm, address, &prev_vma);
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if (!vma || address < vma->vm_start)
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goto check_expansion;
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/*
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* Ok, we have a good vm_area for this memory access. We still need to
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* check the access permissions.
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*/
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good_area:
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if ((vma->vm_flags & acc_type) != acc_type)
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goto bad_area;
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/*
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* If for any reason at all we couldn't handle the fault, make
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* sure we exit gracefully rather than endlessly redo the
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* fault.
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*/
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fault = handle_mm_fault(vma, address, flags);
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if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
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return;
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if (unlikely(fault & VM_FAULT_ERROR)) {
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/*
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* We hit a shared mapping outside of the file, or some
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* other thing happened to us that made us unable to
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* handle the page fault gracefully.
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*/
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if (fault & VM_FAULT_OOM)
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goto out_of_memory;
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else if (fault & VM_FAULT_SIGSEGV)
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goto bad_area;
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else if (fault & VM_FAULT_SIGBUS)
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goto bad_area;
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BUG();
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}
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if (flags & FAULT_FLAG_ALLOW_RETRY) {
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if (fault & VM_FAULT_MAJOR)
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current->maj_flt++;
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else
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current->min_flt++;
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if (fault & VM_FAULT_RETRY) {
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flags &= ~FAULT_FLAG_ALLOW_RETRY;
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/*
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* No need to up_read(&mm->mmap_sem) as we would
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* have already released it in __lock_page_or_retry
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* in mm/filemap.c.
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*/
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goto retry;
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}
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}
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up_read(&mm->mmap_sem);
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return;
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check_expansion:
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vma = prev_vma;
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if (vma && (expand_stack(vma, address) == 0))
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goto good_area;
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/*
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* Something tried to access memory that isn't in our memory map..
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*/
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bad_area:
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up_read(&mm->mmap_sem);
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if (user_mode(regs)) {
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struct siginfo si;
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show_signal_msg(regs, code, address, tsk, vma);
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switch (code) {
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case 15: /* Data TLB miss fault/Data page fault */
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/* send SIGSEGV when outside of vma */
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if (!vma ||
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address < vma->vm_start || address >= vma->vm_end) {
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si.si_signo = SIGSEGV;
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si.si_code = SEGV_MAPERR;
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break;
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}
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/* send SIGSEGV for wrong permissions */
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if ((vma->vm_flags & acc_type) != acc_type) {
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si.si_signo = SIGSEGV;
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si.si_code = SEGV_ACCERR;
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break;
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}
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/* probably address is outside of mapped file */
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/* fall through */
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case 17: /* NA data TLB miss / page fault */
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case 18: /* Unaligned access - PCXS only */
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si.si_signo = SIGBUS;
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si.si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
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break;
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case 16: /* Non-access instruction TLB miss fault */
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case 26: /* PCXL: Data memory access rights trap */
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default:
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si.si_signo = SIGSEGV;
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si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
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break;
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}
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si.si_errno = 0;
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si.si_addr = (void __user *) address;
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force_sig_info(si.si_signo, &si, current);
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return;
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}
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no_context:
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if (!user_mode(regs) && fixup_exception(regs)) {
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return;
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}
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parisc_terminate("Bad Address (null pointer deref?)", regs, code, address);
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out_of_memory:
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up_read(&mm->mmap_sem);
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if (!user_mode(regs))
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goto no_context;
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pagefault_out_of_memory();
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}
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