463 lines
14 KiB
C
463 lines
14 KiB
C
/*
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* Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
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* Copyright 2001-2012 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _POWERPC_EEH_H
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#define _POWERPC_EEH_H
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#ifdef __KERNEL__
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/string.h>
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#include <linux/time.h>
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#include <linux/atomic.h>
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#include <uapi/asm/eeh.h>
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struct pci_dev;
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struct pci_bus;
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struct pci_dn;
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#ifdef CONFIG_EEH
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/* EEH subsystem flags */
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#define EEH_ENABLED 0x01 /* EEH enabled */
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#define EEH_FORCE_DISABLED 0x02 /* EEH disabled */
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#define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */
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#define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */
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#define EEH_VALID_PE_ZERO 0x10 /* PE#0 is valid */
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#define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */
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#define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */
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/*
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* Delay for PE reset, all in ms
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*
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* PCI specification has reset hold time of 100 milliseconds.
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* We have 250 milliseconds here. The PCI bus settlement time
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* is specified as 1.5 seconds and we have 1.8 seconds.
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*/
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#define EEH_PE_RST_HOLD_TIME 250
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#define EEH_PE_RST_SETTLE_TIME 1800
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/*
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* The struct is used to trace PE related EEH functionality.
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* In theory, there will have one instance of the struct to
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* be created against particular PE. In nature, PEs correlate
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* to each other. the struct has to reflect that hierarchy in
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* order to easily pick up those affected PEs when one particular
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* PE has EEH errors.
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*
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* Also, one particular PE might be composed of PCI device, PCI
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* bus and its subordinate components. The struct also need ship
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* the information. Further more, one particular PE is only meaingful
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* in the corresponding PHB. Therefore, the root PEs should be created
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* against existing PHBs in on-to-one fashion.
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*/
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#define EEH_PE_INVALID (1 << 0) /* Invalid */
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#define EEH_PE_PHB (1 << 1) /* PHB PE */
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#define EEH_PE_DEVICE (1 << 2) /* Device PE */
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#define EEH_PE_BUS (1 << 3) /* Bus PE */
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#define EEH_PE_VF (1 << 4) /* VF PE */
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#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
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#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
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#define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */
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#define EEH_PE_RESET (1 << 3) /* PE reset in progress */
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#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
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#define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */
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#define EEH_PE_REMOVED (1 << 10) /* Removed permanently */
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#define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */
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struct eeh_pe {
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int type; /* PE type: PHB/Bus/Device */
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int state; /* PE EEH dependent mode */
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int config_addr; /* Traditional PCI address */
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int addr; /* PE configuration address */
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struct pci_controller *phb; /* Associated PHB */
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struct pci_bus *bus; /* Top PCI bus for bus PE */
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int check_count; /* Times of ignored error */
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int freeze_count; /* Times of froze up */
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struct timeval tstamp; /* Time on first-time freeze */
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int false_positives; /* Times of reported #ff's */
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atomic_t pass_dev_cnt; /* Count of passed through devs */
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struct eeh_pe *parent; /* Parent PE */
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void *data; /* PE auxillary data */
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struct list_head child_list; /* Link PE to the child list */
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struct list_head edevs; /* Link list of EEH devices */
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struct list_head child; /* Child PEs */
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};
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#define eeh_pe_for_each_dev(pe, edev, tmp) \
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list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
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static inline bool eeh_pe_passed(struct eeh_pe *pe)
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{
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return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
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}
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/*
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* The struct is used to trace EEH state for the associated
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* PCI device node or PCI device. In future, it might
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* represent PE as well so that the EEH device to form
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* another tree except the currently existing tree of PCI
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* buses and PCI devices
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*/
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#define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
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#define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
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#define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
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#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
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#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
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#define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
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#define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
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#define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
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struct eeh_dev {
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int mode; /* EEH mode */
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int class_code; /* Class code of the device */
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int config_addr; /* Config address */
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int pe_config_addr; /* PE config address */
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u32 config_space[16]; /* Saved PCI config space */
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int pcix_cap; /* Saved PCIx capability */
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int pcie_cap; /* Saved PCIe capability */
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int aer_cap; /* Saved AER capability */
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int af_cap; /* Saved AF capability */
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struct eeh_pe *pe; /* Associated PE */
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struct list_head list; /* Form link list in the PE */
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struct list_head rmv_list; /* Record the removed edevs */
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struct pci_controller *phb; /* Associated PHB */
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struct pci_dn *pdn; /* Associated PCI device node */
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struct pci_dev *pdev; /* Associated PCI device */
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bool in_error; /* Error flag for edev */
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struct pci_dev *physfn; /* Associated SRIOV PF */
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struct pci_bus *bus; /* PCI bus for partial hotplug */
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};
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static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
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{
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return edev ? edev->pdn : NULL;
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}
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static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
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{
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return edev ? edev->pdev : NULL;
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}
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static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
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{
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return edev ? edev->pe : NULL;
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}
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/* Return values from eeh_ops::next_error */
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enum {
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EEH_NEXT_ERR_NONE = 0,
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EEH_NEXT_ERR_INF,
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EEH_NEXT_ERR_FROZEN_PE,
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EEH_NEXT_ERR_FENCED_PHB,
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EEH_NEXT_ERR_DEAD_PHB,
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EEH_NEXT_ERR_DEAD_IOC
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};
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/*
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* The struct is used to trace the registered EEH operation
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* callback functions. Actually, those operation callback
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* functions are heavily platform dependent. That means the
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* platform should register its own EEH operation callback
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* functions before any EEH further operations.
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*/
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#define EEH_OPT_DISABLE 0 /* EEH disable */
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#define EEH_OPT_ENABLE 1 /* EEH enable */
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#define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
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#define EEH_OPT_THAW_DMA 3 /* DMA enable */
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#define EEH_OPT_FREEZE_PE 4 /* Freeze PE */
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#define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
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#define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
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#define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
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#define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
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#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
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#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
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#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
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#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
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#define EEH_RESET_HOT 1 /* Hot reset */
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#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
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#define EEH_LOG_TEMP 1 /* EEH temporary error log */
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#define EEH_LOG_PERM 2 /* EEH permanent error log */
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struct eeh_ops {
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char *name;
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int (*init)(void);
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int (*post_init)(void);
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void* (*probe)(struct pci_dn *pdn, void *data);
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int (*set_option)(struct eeh_pe *pe, int option);
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int (*get_pe_addr)(struct eeh_pe *pe);
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int (*get_state)(struct eeh_pe *pe, int *state);
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int (*reset)(struct eeh_pe *pe, int option);
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int (*wait_state)(struct eeh_pe *pe, int max_wait);
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int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
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int (*configure_bridge)(struct eeh_pe *pe);
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int (*err_inject)(struct eeh_pe *pe, int type, int func,
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unsigned long addr, unsigned long mask);
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int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
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int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
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int (*next_error)(struct eeh_pe **pe);
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int (*restore_config)(struct pci_dn *pdn);
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};
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extern int eeh_subsystem_flags;
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extern int eeh_max_freezes;
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extern struct eeh_ops *eeh_ops;
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extern raw_spinlock_t confirm_error_lock;
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static inline void eeh_add_flag(int flag)
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{
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eeh_subsystem_flags |= flag;
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}
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static inline void eeh_clear_flag(int flag)
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{
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eeh_subsystem_flags &= ~flag;
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}
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static inline bool eeh_has_flag(int flag)
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{
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return !!(eeh_subsystem_flags & flag);
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}
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static inline bool eeh_enabled(void)
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{
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if (eeh_has_flag(EEH_FORCE_DISABLED) ||
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!eeh_has_flag(EEH_ENABLED))
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return false;
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return true;
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}
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static inline void eeh_serialize_lock(unsigned long *flags)
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{
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raw_spin_lock_irqsave(&confirm_error_lock, *flags);
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}
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static inline void eeh_serialize_unlock(unsigned long flags)
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{
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raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
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}
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typedef void *(*eeh_traverse_func)(void *data, void *flag);
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void eeh_set_pe_aux_size(int size);
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int eeh_phb_pe_create(struct pci_controller *phb);
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struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
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struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
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int eeh_add_to_parent_pe(struct eeh_dev *edev);
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int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
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void eeh_pe_update_time_stamp(struct eeh_pe *pe);
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void *eeh_pe_traverse(struct eeh_pe *root,
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eeh_traverse_func fn, void *flag);
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void *eeh_pe_dev_traverse(struct eeh_pe *root,
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eeh_traverse_func fn, void *flag);
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void eeh_pe_restore_bars(struct eeh_pe *pe);
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const char *eeh_pe_loc_get(struct eeh_pe *pe);
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struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
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struct eeh_dev *eeh_dev_init(struct pci_dn *pdn);
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void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
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int eeh_init(void);
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int __init eeh_ops_register(struct eeh_ops *ops);
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int __exit eeh_ops_unregister(const char *name);
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int eeh_check_failure(const volatile void __iomem *token);
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int eeh_dev_check_failure(struct eeh_dev *edev);
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void eeh_addr_cache_build(void);
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void eeh_add_device_early(struct pci_dn *);
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void eeh_add_device_tree_early(struct pci_dn *);
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void eeh_add_device_late(struct pci_dev *);
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void eeh_add_device_tree_late(struct pci_bus *);
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void eeh_add_sysfs_files(struct pci_bus *);
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void eeh_remove_device(struct pci_dev *);
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int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
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int eeh_pe_reset_and_recover(struct eeh_pe *pe);
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int eeh_dev_open(struct pci_dev *pdev);
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void eeh_dev_release(struct pci_dev *pdev);
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struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
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int eeh_pe_set_option(struct eeh_pe *pe, int option);
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int eeh_pe_get_state(struct eeh_pe *pe);
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int eeh_pe_reset(struct eeh_pe *pe, int option);
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int eeh_pe_configure(struct eeh_pe *pe);
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int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
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unsigned long addr, unsigned long mask);
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/**
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* EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
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*
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* If this macro yields TRUE, the caller relays to eeh_check_failure()
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* which does further tests out of line.
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*/
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#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
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/*
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* Reads from a device which has been isolated by EEH will return
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* all 1s. This macro gives an all-1s value of the given size (in
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* bytes: 1, 2, or 4) for comparing with the result of a read.
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*/
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#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
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#else /* !CONFIG_EEH */
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static inline bool eeh_enabled(void)
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{
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return false;
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}
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static inline int eeh_init(void)
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{
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return 0;
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}
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static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
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{
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return NULL;
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}
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static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
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static inline int eeh_check_failure(const volatile void __iomem *token)
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{
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return 0;
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}
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#define eeh_dev_check_failure(x) (0)
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static inline void eeh_addr_cache_build(void) { }
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static inline void eeh_add_device_early(struct pci_dn *pdn) { }
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static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
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static inline void eeh_add_device_late(struct pci_dev *dev) { }
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static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
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static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
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static inline void eeh_remove_device(struct pci_dev *dev) { }
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#define EEH_POSSIBLE_ERROR(val, type) (0)
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#define EEH_IO_ERROR_VALUE(size) (-1UL)
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#endif /* CONFIG_EEH */
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#ifdef CONFIG_PPC64
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/*
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* MMIO read/write operations with EEH support.
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*/
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static inline u8 eeh_readb(const volatile void __iomem *addr)
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{
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u8 val = in_8(addr);
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if (EEH_POSSIBLE_ERROR(val, u8))
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eeh_check_failure(addr);
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return val;
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}
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static inline u16 eeh_readw(const volatile void __iomem *addr)
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{
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u16 val = in_le16(addr);
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if (EEH_POSSIBLE_ERROR(val, u16))
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eeh_check_failure(addr);
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return val;
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}
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static inline u32 eeh_readl(const volatile void __iomem *addr)
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{
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u32 val = in_le32(addr);
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if (EEH_POSSIBLE_ERROR(val, u32))
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eeh_check_failure(addr);
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return val;
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}
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static inline u64 eeh_readq(const volatile void __iomem *addr)
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{
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u64 val = in_le64(addr);
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if (EEH_POSSIBLE_ERROR(val, u64))
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eeh_check_failure(addr);
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return val;
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}
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static inline u16 eeh_readw_be(const volatile void __iomem *addr)
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{
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u16 val = in_be16(addr);
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if (EEH_POSSIBLE_ERROR(val, u16))
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eeh_check_failure(addr);
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return val;
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}
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static inline u32 eeh_readl_be(const volatile void __iomem *addr)
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{
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u32 val = in_be32(addr);
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if (EEH_POSSIBLE_ERROR(val, u32))
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eeh_check_failure(addr);
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return val;
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}
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static inline u64 eeh_readq_be(const volatile void __iomem *addr)
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{
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u64 val = in_be64(addr);
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if (EEH_POSSIBLE_ERROR(val, u64))
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eeh_check_failure(addr);
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return val;
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}
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static inline void eeh_memcpy_fromio(void *dest, const
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volatile void __iomem *src,
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unsigned long n)
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{
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_memcpy_fromio(dest, src, n);
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/* Look for ffff's here at dest[n]. Assume that at least 4 bytes
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* were copied. Check all four bytes.
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*/
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if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
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eeh_check_failure(src);
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}
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/* in-string eeh macros */
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static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
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int ns)
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{
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_insb(addr, buf, ns);
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if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
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eeh_check_failure(addr);
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}
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static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
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int ns)
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{
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_insw(addr, buf, ns);
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if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
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eeh_check_failure(addr);
|
|
}
|
|
|
|
static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
|
|
int nl)
|
|
{
|
|
_insl(addr, buf, nl);
|
|
if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
|
|
eeh_check_failure(addr);
|
|
}
|
|
|
|
#endif /* CONFIG_PPC64 */
|
|
#endif /* __KERNEL__ */
|
|
#endif /* _POWERPC_EEH_H */
|