424 lines
11 KiB
C
424 lines
11 KiB
C
/*
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* PowerNV cpuidle code
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*
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* Copyright 2015 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/device.h>
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#include <linux/cpu.h>
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#include <asm/firmware.h>
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#include <asm/machdep.h>
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#include <asm/opal.h>
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#include <asm/cputhreads.h>
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#include <asm/cpuidle.h>
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#include <asm/code-patching.h>
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#include <asm/smp.h>
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#include "powernv.h"
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#include "subcore.h"
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/* Power ISA 3.0 allows for stop states 0x0 - 0xF */
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#define MAX_STOP_STATE 0xF
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static u32 supported_cpuidle_states;
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static int pnv_save_sprs_for_deep_states(void)
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{
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int cpu;
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int rc;
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/*
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* hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across
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* all cpus at boot. Get these reg values of current cpu and use the
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* same across all cpus.
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*/
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uint64_t lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1;
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uint64_t hid0_val = mfspr(SPRN_HID0);
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uint64_t hid1_val = mfspr(SPRN_HID1);
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uint64_t hid4_val = mfspr(SPRN_HID4);
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uint64_t hid5_val = mfspr(SPRN_HID5);
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uint64_t hmeer_val = mfspr(SPRN_HMEER);
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for_each_possible_cpu(cpu) {
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uint64_t pir = get_hard_smp_processor_id(cpu);
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uint64_t hsprg0_val = (uint64_t)&paca[cpu];
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if (!cpu_has_feature(CPU_FTR_ARCH_300)) {
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/*
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* HSPRG0 is used to store the cpu's pointer to paca.
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* Hence last 3 bits are guaranteed to be 0. Program
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* slw to restore HSPRG0 with 63rd bit set, so that
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* when a thread wakes up at 0x100 we can use this bit
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* to distinguish between fastsleep and deep winkle.
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* This is not necessary with stop/psscr since PLS
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* field of psscr indicates which state we are waking
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* up from.
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*/
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hsprg0_val |= 1;
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}
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rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);
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if (rc != 0)
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return rc;
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/* HIDs are per core registers */
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if (cpu_thread_in_core(cpu) == 0) {
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rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val);
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if (rc != 0)
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return rc;
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}
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}
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return 0;
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}
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static void pnv_alloc_idle_core_states(void)
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{
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int i, j;
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int nr_cores = cpu_nr_cores();
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u32 *core_idle_state;
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/*
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* core_idle_state - First 8 bits track the idle state of each thread
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* of the core. The 8th bit is the lock bit. Initially all thread bits
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* are set. They are cleared when the thread enters deep idle state
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* like sleep and winkle. Initially the lock bit is cleared.
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* The lock bit has 2 purposes
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* a. While the first thread is restoring core state, it prevents
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* other threads in the core from switching to process context.
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* b. While the last thread in the core is saving the core state, it
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* prevents a different thread from waking up.
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*/
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for (i = 0; i < nr_cores; i++) {
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int first_cpu = i * threads_per_core;
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int node = cpu_to_node(first_cpu);
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core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, node);
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*core_idle_state = PNV_CORE_IDLE_THREAD_BITS;
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for (j = 0; j < threads_per_core; j++) {
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int cpu = first_cpu + j;
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paca[cpu].core_idle_state_ptr = core_idle_state;
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paca[cpu].thread_idle_state = PNV_THREAD_RUNNING;
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paca[cpu].thread_mask = 1 << j;
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}
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}
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update_subcore_sibling_mask();
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if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT)
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pnv_save_sprs_for_deep_states();
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}
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u32 pnv_get_supported_cpuidle_states(void)
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{
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return supported_cpuidle_states;
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}
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EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states);
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static void pnv_fastsleep_workaround_apply(void *info)
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{
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int rc;
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int *err = info;
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rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP,
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OPAL_CONFIG_IDLE_APPLY);
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if (rc)
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*err = 1;
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}
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/*
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* Used to store fastsleep workaround state
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* 0 - Workaround applied/undone at fastsleep entry/exit path (Default)
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* 1 - Workaround applied once, never undone.
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*/
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static u8 fastsleep_workaround_applyonce;
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static ssize_t show_fastsleep_workaround_applyonce(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sprintf(buf, "%u\n", fastsleep_workaround_applyonce);
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}
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static ssize_t store_fastsleep_workaround_applyonce(struct device *dev,
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struct device_attribute *attr, const char *buf,
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size_t count)
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{
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cpumask_t primary_thread_mask;
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int err;
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u8 val;
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if (kstrtou8(buf, 0, &val) || val != 1)
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return -EINVAL;
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if (fastsleep_workaround_applyonce == 1)
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return count;
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/*
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* fastsleep_workaround_applyonce = 1 implies
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* fastsleep workaround needs to be left in 'applied' state on all
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* the cores. Do this by-
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* 1. Patching out the call to 'undo' workaround in fastsleep exit path
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* 2. Sending ipi to all the cores which have at least one online thread
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* 3. Patching out the call to 'apply' workaround in fastsleep entry
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* path
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* There is no need to send ipi to cores which have all threads
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* offlined, as last thread of the core entering fastsleep or deeper
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* state would have applied workaround.
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*/
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err = patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_exit,
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PPC_INST_NOP);
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if (err) {
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pr_err("fastsleep_workaround_applyonce change failed while patching pnv_fastsleep_workaround_at_exit");
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goto fail;
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}
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get_online_cpus();
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primary_thread_mask = cpu_online_cores_map();
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on_each_cpu_mask(&primary_thread_mask,
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pnv_fastsleep_workaround_apply,
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&err, 1);
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put_online_cpus();
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if (err) {
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pr_err("fastsleep_workaround_applyonce change failed while running pnv_fastsleep_workaround_apply");
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goto fail;
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}
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err = patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_entry,
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PPC_INST_NOP);
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if (err) {
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pr_err("fastsleep_workaround_applyonce change failed while patching pnv_fastsleep_workaround_at_entry");
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goto fail;
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}
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fastsleep_workaround_applyonce = 1;
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return count;
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fail:
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return -EIO;
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}
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static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
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show_fastsleep_workaround_applyonce,
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store_fastsleep_workaround_applyonce);
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/*
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* Used for ppc_md.power_save which needs a function with no parameters
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*/
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static void power9_idle(void)
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{
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/* Requesting stop state 0 */
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power9_idle_stop(0);
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}
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/*
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* First deep stop state. Used to figure out when to save/restore
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* hypervisor context.
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*/
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u64 pnv_first_deep_stop_state = MAX_STOP_STATE;
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/*
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* Deepest stop idle state. Used when a cpu is offlined
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*/
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u64 pnv_deepest_stop_state;
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/*
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* Power ISA 3.0 idle initialization.
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*
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* POWER ISA 3.0 defines a new SPR Processor stop Status and Control
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* Register (PSSCR) to control idle behavior.
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*
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* PSSCR layout:
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* ----------------------------------------------------------
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* | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL |
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* ----------------------------------------------------------
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* 0 4 41 42 43 44 48 54 56 60
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*
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* PSSCR key fields:
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* Bits 0:3 - Power-Saving Level Status (PLS). This field indicates the
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* lowest power-saving state the thread entered since stop instruction was
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* last executed.
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*
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* Bit 41 - Status Disable(SD)
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* 0 - Shows PLS entries
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* 1 - PLS entries are all 0
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*
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* Bit 42 - Enable State Loss
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* 0 - No state is lost irrespective of other fields
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* 1 - Allows state loss
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*
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* Bit 43 - Exit Criterion
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* 0 - Exit from power-save mode on any interrupt
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* 1 - Exit from power-save mode controlled by LPCR's PECE bits
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*
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* Bits 44:47 - Power-Saving Level Limit
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* This limits the power-saving level that can be entered into.
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*
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* Bits 60:63 - Requested Level
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* Used to specify which power-saving level must be entered on executing
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* stop instruction
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*
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* @np: /ibm,opal/power-mgt device node
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* @flags: cpu-idle-state-flags array
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* @dt_idle_states: Number of idle state entries
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* Returns 0 on success
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*/
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static int __init pnv_arch300_idle_init(struct device_node *np, u32 *flags,
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int dt_idle_states)
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{
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u64 *psscr_val = NULL;
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int rc = 0, i;
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psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val),
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GFP_KERNEL);
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if (!psscr_val) {
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rc = -1;
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goto out;
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}
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if (of_property_read_u64_array(np,
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"ibm,cpu-idle-state-psscr",
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psscr_val, dt_idle_states)) {
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pr_warn("cpuidle-powernv: missing ibm,cpu-idle-states-psscr in DT\n");
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rc = -1;
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goto out;
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}
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/*
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* Set pnv_first_deep_stop_state and pnv_deepest_stop_state.
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* pnv_first_deep_stop_state should be set to the first stop
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* level to cause hypervisor state loss.
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* pnv_deepest_stop_state should be set to the deepest stop
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* stop state.
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*/
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pnv_first_deep_stop_state = MAX_STOP_STATE;
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for (i = 0; i < dt_idle_states; i++) {
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u64 psscr_rl = psscr_val[i] & PSSCR_RL_MASK;
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if ((flags[i] & OPAL_PM_LOSE_FULL_CONTEXT) &&
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(pnv_first_deep_stop_state > psscr_rl))
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pnv_first_deep_stop_state = psscr_rl;
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if (pnv_deepest_stop_state < psscr_rl)
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pnv_deepest_stop_state = psscr_rl;
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}
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out:
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kfree(psscr_val);
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return rc;
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}
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/*
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* Probe device tree for supported idle states
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*/
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static void __init pnv_probe_idle_states(void)
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{
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struct device_node *np;
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int dt_idle_states;
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u32 *flags = NULL;
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int i;
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np = of_find_node_by_path("/ibm,opal/power-mgt");
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if (!np) {
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pr_warn("opal: PowerMgmt Node not found\n");
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goto out;
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}
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dt_idle_states = of_property_count_u32_elems(np,
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"ibm,cpu-idle-state-flags");
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if (dt_idle_states < 0) {
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pr_warn("cpuidle-powernv: no idle states found in the DT\n");
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goto out;
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}
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flags = kcalloc(dt_idle_states, sizeof(*flags), GFP_KERNEL);
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if (of_property_read_u32_array(np,
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"ibm,cpu-idle-state-flags", flags, dt_idle_states)) {
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pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n");
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goto out;
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}
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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if (pnv_arch300_idle_init(np, flags, dt_idle_states))
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goto out;
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}
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for (i = 0; i < dt_idle_states; i++)
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supported_cpuidle_states |= flags[i];
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out:
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kfree(flags);
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}
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static int __init pnv_init_idle_states(void)
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{
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supported_cpuidle_states = 0;
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if (cpuidle_disable != IDLE_NO_OVERRIDE)
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goto out;
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pnv_probe_idle_states();
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if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
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patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_entry,
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PPC_INST_NOP);
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patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_exit,
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PPC_INST_NOP);
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} else {
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/*
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* OPAL_PM_SLEEP_ENABLED_ER1 is set. It indicates that
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* workaround is needed to use fastsleep. Provide sysfs
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* control to choose how this workaround has to be applied.
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*/
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device_create_file(cpu_subsys.dev_root,
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&dev_attr_fastsleep_workaround_applyonce);
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}
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pnv_alloc_idle_core_states();
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if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED)
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ppc_md.power_save = power7_idle;
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else if (supported_cpuidle_states & OPAL_PM_STOP_INST_FAST)
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ppc_md.power_save = power9_idle;
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out:
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return 0;
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}
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machine_subsys_initcall(powernv, pnv_init_idle_states);
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