386 lines
10 KiB
C
386 lines
10 KiB
C
/*
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* Copyright 2014-2016 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <asm/pci-bridge.h>
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#include <asm/pnv-pci.h>
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#include <asm/opal.h>
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#include <misc/cxl.h>
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#include "pci.h"
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struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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return of_node_get(hose->dn);
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}
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EXPORT_SYMBOL(pnv_pci_get_phb_node);
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int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct pnv_ioda_pe *pe;
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int rc;
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pe = pnv_ioda_get_pe(dev);
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if (!pe)
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return -ENODEV;
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pe_info(pe, "Switching PHB to CXL\n");
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rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
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if (rc == OPAL_UNSUPPORTED)
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dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
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else if (rc)
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dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
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return rc;
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}
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EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
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/* Find PHB for cxl dev and allocate MSI hwirqs?
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* Returns the absolute hardware IRQ number
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*/
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int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
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if (hwirq < 0) {
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dev_warn(&dev->dev, "Failed to find a free MSI\n");
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return -ENOSPC;
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}
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return phb->msi_base + hwirq;
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}
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EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
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void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
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}
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EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
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void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int i, hwirq;
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for (i = 1; i < CXL_IRQ_RANGES; i++) {
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if (!irqs->range[i])
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continue;
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pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
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i, irqs->offset[i],
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irqs->range[i]);
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hwirq = irqs->offset[i] - phb->msi_base;
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
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irqs->range[i]);
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}
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}
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EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
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int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int i, hwirq, try;
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memset(irqs, 0, sizeof(struct cxl_irq_ranges));
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/* 0 is reserved for the multiplexed PSL DSI interrupt */
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for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
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try = num;
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while (try) {
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hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
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if (hwirq >= 0)
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break;
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try /= 2;
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}
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if (!try)
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goto fail;
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irqs->offset[i] = phb->msi_base + hwirq;
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irqs->range[i] = try;
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pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
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i, irqs->offset[i], irqs->range[i]);
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num -= try;
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}
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if (num)
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goto fail;
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return 0;
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fail:
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pnv_cxl_release_hwirq_ranges(irqs, dev);
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return -ENOSPC;
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}
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EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
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int pnv_cxl_get_irq_count(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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return phb->msi_bmp.irq_count;
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}
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EXPORT_SYMBOL(pnv_cxl_get_irq_count);
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int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
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unsigned int virq)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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unsigned int xive_num = hwirq - phb->msi_base;
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struct pnv_ioda_pe *pe;
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int rc;
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if (!(pe = pnv_ioda_get_pe(dev)))
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return -ENODEV;
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/* Assign XIVE to PE */
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rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
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if (rc) {
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pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
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"hwirq 0x%x XIVE 0x%x PE\n",
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pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
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return -EIO;
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}
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pnv_set_msi_irq_chip(phb, virq);
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return 0;
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}
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EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
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#if IS_MODULE(CONFIG_CXL)
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static inline int get_cxl_module(void)
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{
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struct module *cxl_module;
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mutex_lock(&module_mutex);
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cxl_module = find_module("cxl");
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if (cxl_module)
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__module_get(cxl_module);
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mutex_unlock(&module_mutex);
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if (!cxl_module)
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return -ENODEV;
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return 0;
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}
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#else
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static inline int get_cxl_module(void) { return 0; }
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#endif
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/*
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* Sets flags and switches the controller ops to enable the cxl kernel api.
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* Originally the cxl kernel API operated on a virtual PHB, but certain cards
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* such as the Mellanox CX4 use a peer model instead and for these cards the
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* cxl kernel api will operate on the real PHB.
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*/
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int pnv_cxl_enable_phb_kernel_api(struct pci_controller *hose, bool enable)
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{
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struct pnv_phb *phb = hose->private_data;
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int rc;
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if (!enable) {
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/*
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* Once cxl mode is enabled on the PHB, there is currently no
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* known safe method to disable it again, and trying risks a
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* checkstop. If we can find a way to safely disable cxl mode
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* in the future we can revisit this, but for now the only sane
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* thing to do is to refuse to disable cxl mode:
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*/
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return -EPERM;
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}
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/*
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* Hold a reference to the cxl module since several PHB operations now
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* depend on it, and it would be insane to allow it to be removed so
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* long as we are in this mode (and since we can't safely disable this
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* mode once enabled...).
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*/
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rc = get_cxl_module();
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if (rc)
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return rc;
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phb->flags |= PNV_PHB_FLAG_CXL;
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hose->controller_ops = pnv_cxl_cx4_ioda_controller_ops;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pnv_cxl_enable_phb_kernel_api);
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bool pnv_pci_on_cxl_phb(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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return !!(phb->flags & PNV_PHB_FLAG_CXL);
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}
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EXPORT_SYMBOL_GPL(pnv_pci_on_cxl_phb);
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struct cxl_afu *pnv_cxl_phb_to_afu(struct pci_controller *hose)
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{
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struct pnv_phb *phb = hose->private_data;
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return (struct cxl_afu *)phb->cxl_afu;
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}
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EXPORT_SYMBOL_GPL(pnv_cxl_phb_to_afu);
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void pnv_cxl_phb_set_peer_afu(struct pci_dev *dev, struct cxl_afu *afu)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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phb->cxl_afu = afu;
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}
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EXPORT_SYMBOL_GPL(pnv_cxl_phb_set_peer_afu);
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/*
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* In the peer cxl model, the XSL/PSL is physical function 0, and will be used
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* by other functions on the device for memory access and interrupts. When the
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* other functions are enabled we explicitly take a reference on the cxl
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* function since they will use it, and allocate a default context associated
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* with that function just like the vPHB model of the cxl kernel API.
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*/
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bool pnv_cxl_enable_device_hook(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct cxl_afu *afu = phb->cxl_afu;
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if (!pnv_pci_enable_device_hook(dev))
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return false;
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/* No special handling for the cxl function, which is always PF 0 */
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if (PCI_FUNC(dev->devfn) == 0)
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return true;
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if (!afu) {
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dev_WARN(&dev->dev, "Attempted to enable function > 0 on CXL PHB without a peer AFU\n");
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return false;
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}
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dev_info(&dev->dev, "Enabling function on CXL enabled PHB with peer AFU\n");
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/* Make sure the peer AFU can't go away while this device is active */
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cxl_afu_get(afu);
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return cxl_pci_associate_default_context(dev, afu);
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}
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void pnv_cxl_disable_device(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct cxl_afu *afu = phb->cxl_afu;
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/* No special handling for cxl function: */
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if (PCI_FUNC(dev->devfn) == 0)
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return;
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cxl_pci_disable_device(dev);
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cxl_afu_put(afu);
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}
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/*
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* This is a special version of pnv_setup_msi_irqs for cards in cxl mode. This
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* function handles setting up the IVTE entries for the XSL to use.
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*
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* We are currently not filling out the MSIX table, since the only currently
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* supported adapter (CX4) uses a custom MSIX table format in cxl mode and it
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* is up to their driver to fill that out. In the future we may fill out the
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* MSIX table (and change the IVTE entries to be an index to the MSIX table)
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* for adapters implementing the Full MSI-X mode described in the CAIA.
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*/
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int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct msi_desc *entry;
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struct cxl_context *ctx = NULL;
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unsigned int virq;
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int hwirq;
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int afu_irq = 0;
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int rc;
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if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
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return -ENODEV;
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if (pdev->no_64bit_msi && !phb->msi32_support)
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return -ENODEV;
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rc = cxl_cx4_setup_msi_irqs(pdev, nvec, type);
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if (rc)
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return rc;
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for_each_pci_msi_entry(entry, pdev) {
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if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
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pr_warn("%s: Supports only 64-bit MSIs\n",
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pci_name(pdev));
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return -ENXIO;
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}
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hwirq = cxl_next_msi_hwirq(pdev, &ctx, &afu_irq);
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if (WARN_ON(hwirq <= 0))
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return (hwirq ? hwirq : -ENOMEM);
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virq = irq_create_mapping(NULL, hwirq);
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if (!virq) {
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pr_warn("%s: Failed to map cxl mode MSI to linux irq\n",
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pci_name(pdev));
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return -ENOMEM;
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}
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rc = pnv_cxl_ioda_msi_setup(pdev, hwirq, virq);
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if (rc) {
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pr_warn("%s: Failed to setup cxl mode MSI\n", pci_name(pdev));
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irq_dispose_mapping(virq);
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return rc;
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}
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irq_set_msi_desc(virq, entry);
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}
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return 0;
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}
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void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct msi_desc *entry;
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irq_hw_number_t hwirq;
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if (WARN_ON(!phb))
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return;
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for_each_pci_msi_entry(entry, pdev) {
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if (!entry->irq)
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continue;
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hwirq = virq_to_hw(entry->irq);
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irq_set_msi_desc(entry->irq, NULL);
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irq_dispose_mapping(entry->irq);
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}
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cxl_cx4_teardown_msi_irqs(pdev);
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}
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