274 lines
7.2 KiB
C
274 lines
7.2 KiB
C
/*
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* SMP support for PowerNV machines.
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*
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* Copyright 2011 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/cpu.h>
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#include <asm/irq.h>
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#include <asm/smp.h>
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#include <asm/paca.h>
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#include <asm/machdep.h>
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#include <asm/cputable.h>
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#include <asm/firmware.h>
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#include <asm/vdso_datapage.h>
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#include <asm/cputhreads.h>
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#include <asm/xics.h>
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#include <asm/opal.h>
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#include <asm/runlatch.h>
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#include <asm/code-patching.h>
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#include <asm/dbell.h>
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#include <asm/kvm_ppc.h>
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#include <asm/ppc-opcode.h>
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#include "powernv.h"
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#ifdef DEBUG
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#include <asm/udbg.h>
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...) do { } while (0)
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#endif
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static void pnv_smp_setup_cpu(int cpu)
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{
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if (cpu != boot_cpuid)
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xics_setup_cpu();
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#ifdef CONFIG_PPC_DOORBELL
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if (cpu_has_feature(CPU_FTR_DBELL))
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doorbell_setup_this_cpu();
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#endif
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}
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static int pnv_smp_kick_cpu(int nr)
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{
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unsigned int pcpu = get_hard_smp_processor_id(nr);
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unsigned long start_here =
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__pa(ppc_function_entry(generic_secondary_smp_init));
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long rc;
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uint8_t status;
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BUG_ON(nr < 0 || nr >= NR_CPUS);
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/*
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* If we already started or OPAL is not supported, we just
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* kick the CPU via the PACA
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*/
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if (paca[nr].cpu_start || !firmware_has_feature(FW_FEATURE_OPAL))
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goto kick;
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/*
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* At this point, the CPU can either be spinning on the way in
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* from kexec or be inside OPAL waiting to be started for the
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* first time. OPAL v3 allows us to query OPAL to know if it
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* has the CPUs, so we do that
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*/
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rc = opal_query_cpu_status(pcpu, &status);
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if (rc != OPAL_SUCCESS) {
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pr_warn("OPAL Error %ld querying CPU %d state\n", rc, nr);
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return -ENODEV;
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}
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/*
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* Already started, just kick it, probably coming from
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* kexec and spinning
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*/
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if (status == OPAL_THREAD_STARTED)
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goto kick;
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/*
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* Available/inactive, let's kick it
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*/
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if (status == OPAL_THREAD_INACTIVE) {
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pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu);
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rc = opal_start_cpu(pcpu, start_here);
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if (rc != OPAL_SUCCESS) {
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pr_warn("OPAL Error %ld starting CPU %d\n", rc, nr);
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return -ENODEV;
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}
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} else {
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/*
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* An unavailable CPU (or any other unknown status)
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* shouldn't be started. It should also
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* not be in the possible map but currently it can
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* happen
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*/
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pr_devel("OPAL: CPU %d (HW 0x%x) is unavailable"
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" (status %d)...\n", nr, pcpu, status);
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return -ENODEV;
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}
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kick:
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return smp_generic_kick_cpu(nr);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int pnv_smp_cpu_disable(void)
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{
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int cpu = smp_processor_id();
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/* This is identical to pSeries... might consolidate by
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* moving migrate_irqs_away to a ppc_md with default to
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* the generic fixup_irqs. --BenH.
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*/
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set_cpu_online(cpu, false);
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vdso_data->processorCount--;
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if (cpu == boot_cpuid)
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boot_cpuid = cpumask_any(cpu_online_mask);
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xics_migrate_irqs_away();
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return 0;
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}
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static void pnv_smp_cpu_kill_self(void)
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{
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unsigned int cpu;
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unsigned long srr1, wmask;
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u32 idle_states;
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/* Standard hot unplug procedure */
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local_irq_disable();
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idle_task_exit();
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current->active_mm = NULL; /* for sanity */
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cpu = smp_processor_id();
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DBG("CPU%d offline\n", cpu);
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generic_set_cpu_dead(cpu);
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smp_wmb();
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wmask = SRR1_WAKEMASK;
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if (cpu_has_feature(CPU_FTR_ARCH_207S))
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wmask = SRR1_WAKEMASK_P8;
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idle_states = pnv_get_supported_cpuidle_states();
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/* We don't want to take decrementer interrupts while we are offline,
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* so clear LPCR:PECE1. We keep PECE2 (and LPCR_PECE_HVEE on P9)
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* enabled as to let IPIs in.
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*/
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1);
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/*
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* Hard-disable interrupts, and then clear irq_happened flags
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* that we can safely ignore while off-line, since they
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* are for things for which we do no processing when off-line
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* (or in the case of HMI, all the processing we need to do
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* is done in lower-level real-mode code).
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*/
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hard_irq_disable();
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local_paca->irq_happened &= ~(PACA_IRQ_DEC | PACA_IRQ_HMI);
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while (!generic_check_cpu_restart(cpu)) {
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/*
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* Clear IPI flag, since we don't handle IPIs while
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* offline, except for those when changing micro-threading
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* mode, which are handled explicitly below, and those
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* for coming online, which are handled via
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* generic_check_cpu_restart() calls.
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*/
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kvmppc_set_host_ipi(cpu, 0);
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ppc64_runlatch_off();
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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srr1 = power9_idle_stop(pnv_deepest_stop_state);
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else if (idle_states & OPAL_PM_WINKLE_ENABLED)
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srr1 = power7_winkle();
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else if ((idle_states & OPAL_PM_SLEEP_ENABLED) ||
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(idle_states & OPAL_PM_SLEEP_ENABLED_ER1))
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srr1 = power7_sleep();
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else
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srr1 = power7_nap(1);
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ppc64_runlatch_on();
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/*
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* If the SRR1 value indicates that we woke up due to
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* an external interrupt, then clear the interrupt.
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* We clear the interrupt before checking for the
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* reason, so as to avoid a race where we wake up for
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* some other reason, find nothing and clear the interrupt
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* just as some other cpu is sending us an interrupt.
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* If we returned from power7_nap as a result of
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* having finished executing in a KVM guest, then srr1
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* contains 0.
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*/
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if (((srr1 & wmask) == SRR1_WAKEEE) ||
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((srr1 & wmask) == SRR1_WAKEHVI) ||
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(local_paca->irq_happened & PACA_IRQ_EE)) {
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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icp_opal_flush_interrupt();
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else
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icp_native_flush_interrupt();
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} else if ((srr1 & wmask) == SRR1_WAKEHDBELL) {
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unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
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asm volatile(PPC_MSGCLR(%0) : : "r" (msg));
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}
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local_paca->irq_happened &= ~(PACA_IRQ_EE | PACA_IRQ_DBELL);
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smp_mb();
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if (cpu_core_split_required())
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continue;
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if (srr1 && !generic_check_cpu_restart(cpu))
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DBG("CPU%d Unexpected exit while offline !\n", cpu);
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}
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/* Re-enable decrementer interrupts */
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mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_PECE1);
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DBG("CPU%d coming online...\n", cpu);
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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static int pnv_cpu_bootable(unsigned int nr)
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{
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/*
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* Starting with POWER8, the subcore logic relies on all threads of a
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* core being booted so that they can participate in split mode
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* switches. So on those machines we ignore the smt_enabled_at_boot
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* setting (smt-enabled on the kernel command line).
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_207S))
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return 1;
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return smp_generic_cpu_bootable(nr);
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}
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static struct smp_ops_t pnv_smp_ops = {
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.message_pass = smp_muxed_ipi_message_pass,
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.cause_ipi = NULL, /* Filled at runtime by xics_smp_probe() */
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.probe = xics_smp_probe,
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.kick_cpu = pnv_smp_kick_cpu,
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.setup_cpu = pnv_smp_setup_cpu,
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.cpu_bootable = pnv_cpu_bootable,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_disable = pnv_smp_cpu_disable,
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.cpu_die = generic_cpu_die,
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#endif /* CONFIG_HOTPLUG_CPU */
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};
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/* This is called very early during platform setup_arch */
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void __init pnv_smp_init(void)
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{
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smp_ops = &pnv_smp_ops;
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#ifdef CONFIG_HOTPLUG_CPU
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ppc_md.cpu_die = pnv_smp_cpu_kill_self;
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#endif
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}
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