436 lines
10 KiB
C
436 lines
10 KiB
C
/*
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* Freescale LBC and UPM routines.
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*
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* Copyright © 2007-2008 MontaVista Software, Inc.
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* Copyright © 2010 Freescale Semiconductor
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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* Author: Jack Lan <Jack.Lan@freescale.com>
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* Author: Roy Zang <tie-fei.zang@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/mod_devicetable.h>
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#include <linux/syscore_ops.h>
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#include <asm/prom.h>
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#include <asm/fsl_lbc.h>
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static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
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struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
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EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
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/**
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* fsl_lbc_addr - convert the base address
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* @addr_base: base address of the memory bank
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*
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* This function converts a base address of lbc into the right format for the
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* BR register. If the SOC has eLBC then it returns 32bit physical address
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* else it convers a 34bit local bus physical address to correct format of
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* 32bit address for BR register (Example: MPC8641).
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*/
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u32 fsl_lbc_addr(phys_addr_t addr_base)
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{
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struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
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u32 addr = addr_base & 0xffff8000;
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if (of_device_is_compatible(np, "fsl,elbc"))
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return addr;
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return addr | ((addr_base & 0x300000000ull) >> 19);
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}
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EXPORT_SYMBOL(fsl_lbc_addr);
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/**
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* fsl_lbc_find - find Localbus bank
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* @addr_base: base address of the memory bank
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*
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* This function walks LBC banks comparing "Base address" field of the BR
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* registers with the supplied addr_base argument. When bases match this
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* function returns bank number (starting with 0), otherwise it returns
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* appropriate errno value.
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*/
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int fsl_lbc_find(phys_addr_t addr_base)
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{
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int i;
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struct fsl_lbc_regs __iomem *lbc;
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if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
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return -ENODEV;
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lbc = fsl_lbc_ctrl_dev->regs;
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for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
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u32 br = in_be32(&lbc->bank[i].br);
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u32 or = in_be32(&lbc->bank[i].or);
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if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
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return i;
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}
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return -ENOENT;
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}
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EXPORT_SYMBOL(fsl_lbc_find);
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/**
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* fsl_upm_find - find pre-programmed UPM via base address
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* @addr_base: base address of the memory bank controlled by the UPM
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* @upm: pointer to the allocated fsl_upm structure
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*
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* This function fills fsl_upm structure so you can use it with the rest of
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* UPM API. On success this function returns 0, otherwise it returns
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* appropriate errno value.
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*/
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int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
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{
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int bank;
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u32 br;
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struct fsl_lbc_regs __iomem *lbc;
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bank = fsl_lbc_find(addr_base);
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if (bank < 0)
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return bank;
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if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
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return -ENODEV;
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lbc = fsl_lbc_ctrl_dev->regs;
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br = in_be32(&lbc->bank[bank].br);
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switch (br & BR_MSEL) {
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case BR_MS_UPMA:
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upm->mxmr = &lbc->mamr;
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break;
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case BR_MS_UPMB:
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upm->mxmr = &lbc->mbmr;
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break;
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case BR_MS_UPMC:
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upm->mxmr = &lbc->mcmr;
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break;
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default:
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return -EINVAL;
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}
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switch (br & BR_PS) {
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case BR_PS_8:
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upm->width = 8;
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break;
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case BR_PS_16:
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upm->width = 16;
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break;
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case BR_PS_32:
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upm->width = 32;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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EXPORT_SYMBOL(fsl_upm_find);
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/**
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* fsl_upm_run_pattern - actually run an UPM pattern
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* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
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* @io_base: remapped pointer to where memory access should happen
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* @mar: MAR register content during pattern execution
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*
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* This function triggers dummy write to the memory specified by the io_base,
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* thus UPM pattern actually executed. Note that mar usage depends on the
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* pre-programmed AMX bits in the UPM RAM.
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*/
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int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
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{
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int ret = 0;
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unsigned long flags;
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if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
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return -ENODEV;
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spin_lock_irqsave(&fsl_lbc_lock, flags);
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out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
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switch (upm->width) {
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case 8:
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out_8(io_base, 0x0);
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break;
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case 16:
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out_be16(io_base, 0x0);
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break;
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case 32:
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out_be32(io_base, 0x0);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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spin_unlock_irqrestore(&fsl_lbc_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(fsl_upm_run_pattern);
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static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
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struct device_node *node)
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{
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
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/* clear event registers */
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setbits32(&lbc->ltesr, LTESR_CLEAR);
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out_be32(&lbc->lteatr, 0);
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out_be32(&lbc->ltear, 0);
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out_be32(&lbc->lteccr, LTECCR_CLEAR);
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out_be32(&lbc->ltedr, LTEDR_ENABLE);
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/* Set the monitor timeout value to the maximum for erratum A001 */
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if (of_device_is_compatible(node, "fsl,elbc"))
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clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
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return 0;
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}
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/*
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* NOTE: This interrupt is used to report localbus events of various kinds,
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* such as transaction errors on the chipselects.
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*/
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static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
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{
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struct fsl_lbc_ctrl *ctrl = data;
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
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u32 status;
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unsigned long flags;
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spin_lock_irqsave(&fsl_lbc_lock, flags);
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status = in_be32(&lbc->ltesr);
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if (!status) {
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spin_unlock_irqrestore(&fsl_lbc_lock, flags);
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return IRQ_NONE;
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}
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out_be32(&lbc->ltesr, LTESR_CLEAR);
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out_be32(&lbc->lteatr, 0);
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out_be32(&lbc->ltear, 0);
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ctrl->irq_status = status;
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if (status & LTESR_BM)
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dev_err(ctrl->dev, "Local bus monitor time-out: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_WP)
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dev_err(ctrl->dev, "Write protect error: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_ATMW)
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dev_err(ctrl->dev, "Atomic write error: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_ATMR)
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dev_err(ctrl->dev, "Atomic read error: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_CS)
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dev_err(ctrl->dev, "Chip select error: "
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"LTESR 0x%08X\n", status);
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if (status & LTESR_FCT) {
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dev_err(ctrl->dev, "FCM command time-out: "
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"LTESR 0x%08X\n", status);
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smp_wmb();
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wake_up(&ctrl->irq_wait);
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}
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if (status & LTESR_PAR) {
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dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
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"LTESR 0x%08X\n", status);
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smp_wmb();
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wake_up(&ctrl->irq_wait);
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}
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if (status & LTESR_CC) {
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smp_wmb();
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wake_up(&ctrl->irq_wait);
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}
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if (status & ~LTESR_MASK)
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dev_err(ctrl->dev, "Unknown error: "
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"LTESR 0x%08X\n", status);
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spin_unlock_irqrestore(&fsl_lbc_lock, flags);
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return IRQ_HANDLED;
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}
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/*
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* fsl_lbc_ctrl_probe
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*
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* called by device layer when it finds a device matching
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* one our driver can handled. This code allocates all of
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* the resources needed for the controller only. The
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* resources for the NAND banks themselves are allocated
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* in the chip probe function.
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*/
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static int fsl_lbc_ctrl_probe(struct platform_device *dev)
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{
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int ret;
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if (!dev->dev.of_node) {
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dev_err(&dev->dev, "Device OF-Node is NULL");
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return -EFAULT;
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}
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fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
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if (!fsl_lbc_ctrl_dev)
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return -ENOMEM;
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dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
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spin_lock_init(&fsl_lbc_ctrl_dev->lock);
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init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
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fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
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if (!fsl_lbc_ctrl_dev->regs) {
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dev_err(&dev->dev, "failed to get memory region\n");
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ret = -ENODEV;
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goto err;
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}
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fsl_lbc_ctrl_dev->irq[0] = irq_of_parse_and_map(dev->dev.of_node, 0);
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if (!fsl_lbc_ctrl_dev->irq[0]) {
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dev_err(&dev->dev, "failed to get irq resource\n");
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ret = -ENODEV;
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goto err;
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}
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fsl_lbc_ctrl_dev->dev = &dev->dev;
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ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
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if (ret < 0)
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goto err;
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ret = request_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_irq, 0,
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"fsl-lbc", fsl_lbc_ctrl_dev);
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if (ret != 0) {
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dev_err(&dev->dev, "failed to install irq (%d)\n",
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fsl_lbc_ctrl_dev->irq[0]);
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ret = fsl_lbc_ctrl_dev->irq[0];
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goto err;
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}
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fsl_lbc_ctrl_dev->irq[1] = irq_of_parse_and_map(dev->dev.of_node, 1);
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if (fsl_lbc_ctrl_dev->irq[1]) {
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ret = request_irq(fsl_lbc_ctrl_dev->irq[1], fsl_lbc_ctrl_irq,
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IRQF_SHARED, "fsl-lbc-err", fsl_lbc_ctrl_dev);
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if (ret) {
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dev_err(&dev->dev, "failed to install irq (%d)\n",
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fsl_lbc_ctrl_dev->irq[1]);
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ret = fsl_lbc_ctrl_dev->irq[1];
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goto err1;
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}
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}
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/* Enable interrupts for any detected events */
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out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
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return 0;
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err1:
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free_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_dev);
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err:
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iounmap(fsl_lbc_ctrl_dev->regs);
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kfree(fsl_lbc_ctrl_dev);
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fsl_lbc_ctrl_dev = NULL;
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return ret;
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}
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#ifdef CONFIG_SUSPEND
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/* save lbc registers */
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static int fsl_lbc_syscore_suspend(void)
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{
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struct fsl_lbc_ctrl *ctrl;
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struct fsl_lbc_regs __iomem *lbc;
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ctrl = fsl_lbc_ctrl_dev;
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if (!ctrl)
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goto out;
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lbc = ctrl->regs;
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if (!lbc)
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goto out;
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ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
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if (!ctrl->saved_regs)
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return -ENOMEM;
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_memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
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out:
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return 0;
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}
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/* restore lbc registers */
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static void fsl_lbc_syscore_resume(void)
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{
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struct fsl_lbc_ctrl *ctrl;
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struct fsl_lbc_regs __iomem *lbc;
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ctrl = fsl_lbc_ctrl_dev;
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if (!ctrl)
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goto out;
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lbc = ctrl->regs;
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if (!lbc)
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goto out;
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if (ctrl->saved_regs) {
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_memcpy_toio(lbc, ctrl->saved_regs,
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sizeof(struct fsl_lbc_regs));
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kfree(ctrl->saved_regs);
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ctrl->saved_regs = NULL;
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}
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out:
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return;
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}
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#endif /* CONFIG_SUSPEND */
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static const struct of_device_id fsl_lbc_match[] = {
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{ .compatible = "fsl,elbc", },
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{ .compatible = "fsl,pq3-localbus", },
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{ .compatible = "fsl,pq2-localbus", },
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{ .compatible = "fsl,pq2pro-localbus", },
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{},
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};
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#ifdef CONFIG_SUSPEND
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static struct syscore_ops lbc_syscore_pm_ops = {
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.suspend = fsl_lbc_syscore_suspend,
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.resume = fsl_lbc_syscore_resume,
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};
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#endif
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static struct platform_driver fsl_lbc_ctrl_driver = {
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.driver = {
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.name = "fsl-lbc",
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.of_match_table = fsl_lbc_match,
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},
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.probe = fsl_lbc_ctrl_probe,
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};
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static int __init fsl_lbc_init(void)
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{
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#ifdef CONFIG_SUSPEND
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register_syscore_ops(&lbc_syscore_pm_ops);
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#endif
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return platform_driver_register(&fsl_lbc_ctrl_driver);
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}
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subsys_initcall(fsl_lbc_init);
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