281 lines
6.2 KiB
C
281 lines
6.2 KiB
C
/*
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* S390 version
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* Copyright IBM Corp. 1999
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* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
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*
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* Derived from "include/asm-i386/spinlock.h"
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*/
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <linux/smp.h>
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#include <asm/barrier.h>
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#include <asm/processor.h>
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#define SPINLOCK_LOCKVAL (S390_lowcore.spinlock_lockval)
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extern int spin_retry;
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static inline int
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_raw_compare_and_swap(unsigned int *lock, unsigned int old, unsigned int new)
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{
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return __sync_bool_compare_and_swap(lock, old, new);
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}
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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void arch_lock_relax(unsigned int cpu);
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void arch_spin_lock_wait(arch_spinlock_t *);
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int arch_spin_trylock_retry(arch_spinlock_t *);
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void arch_spin_lock_wait_flags(arch_spinlock_t *, unsigned long flags);
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static inline void arch_spin_relax(arch_spinlock_t *lock)
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{
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arch_lock_relax(lock->lock);
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}
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static inline u32 arch_spin_lockval(int cpu)
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{
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return ~cpu;
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}
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static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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return lock.lock == 0;
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}
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static inline int arch_spin_is_locked(arch_spinlock_t *lp)
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{
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return ACCESS_ONCE(lp->lock) != 0;
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}
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static inline int arch_spin_trylock_once(arch_spinlock_t *lp)
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{
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barrier();
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return likely(arch_spin_value_unlocked(*lp) &&
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_raw_compare_and_swap(&lp->lock, 0, SPINLOCK_LOCKVAL));
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}
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static inline void arch_spin_lock(arch_spinlock_t *lp)
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{
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if (!arch_spin_trylock_once(lp))
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arch_spin_lock_wait(lp);
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}
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static inline void arch_spin_lock_flags(arch_spinlock_t *lp,
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unsigned long flags)
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{
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if (!arch_spin_trylock_once(lp))
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arch_spin_lock_wait_flags(lp, flags);
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lp)
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{
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if (!arch_spin_trylock_once(lp))
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return arch_spin_trylock_retry(lp);
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return 1;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lp)
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{
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typecheck(unsigned int, lp->lock);
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asm volatile(
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"st %1,%0\n"
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: "+Q" (lp->lock)
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: "d" (0)
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: "cc", "memory");
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}
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static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
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{
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while (arch_spin_is_locked(lock))
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arch_spin_relax(lock);
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smp_acquire__after_ctrl_dep();
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define arch_read_can_lock(x) ((int)(x)->lock >= 0)
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define arch_write_can_lock(x) ((x)->lock == 0)
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extern int _raw_read_trylock_retry(arch_rwlock_t *lp);
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extern int _raw_write_trylock_retry(arch_rwlock_t *lp);
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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static inline int arch_read_trylock_once(arch_rwlock_t *rw)
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{
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unsigned int old = ACCESS_ONCE(rw->lock);
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return likely((int) old >= 0 &&
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_raw_compare_and_swap(&rw->lock, old, old + 1));
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}
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static inline int arch_write_trylock_once(arch_rwlock_t *rw)
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{
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unsigned int old = ACCESS_ONCE(rw->lock);
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return likely(old == 0 &&
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_raw_compare_and_swap(&rw->lock, 0, 0x80000000));
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}
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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#define __RAW_OP_OR "lao"
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#define __RAW_OP_AND "lan"
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#define __RAW_OP_ADD "laa"
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#define __RAW_LOCK(ptr, op_val, op_string) \
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({ \
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unsigned int old_val; \
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\
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typecheck(unsigned int *, ptr); \
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asm volatile( \
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op_string " %0,%2,%1\n" \
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"bcr 14,0\n" \
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: "=d" (old_val), "+Q" (*ptr) \
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: "d" (op_val) \
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: "cc", "memory"); \
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old_val; \
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})
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#define __RAW_UNLOCK(ptr, op_val, op_string) \
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({ \
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unsigned int old_val; \
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\
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typecheck(unsigned int *, ptr); \
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asm volatile( \
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op_string " %0,%2,%1\n" \
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: "=d" (old_val), "+Q" (*ptr) \
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: "d" (op_val) \
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: "cc", "memory"); \
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old_val; \
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})
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extern void _raw_read_lock_wait(arch_rwlock_t *lp);
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extern void _raw_write_lock_wait(arch_rwlock_t *lp, unsigned int prev);
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned int old;
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old = __RAW_LOCK(&rw->lock, 1, __RAW_OP_ADD);
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if ((int) old < 0)
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_raw_read_lock_wait(rw);
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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__RAW_UNLOCK(&rw->lock, -1, __RAW_OP_ADD);
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned int old;
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old = __RAW_LOCK(&rw->lock, 0x80000000, __RAW_OP_OR);
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if (old != 0)
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_raw_write_lock_wait(rw, old);
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rw->owner = SPINLOCK_LOCKVAL;
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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rw->owner = 0;
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__RAW_UNLOCK(&rw->lock, 0x7fffffff, __RAW_OP_AND);
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}
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#else /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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extern void _raw_read_lock_wait(arch_rwlock_t *lp);
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extern void _raw_write_lock_wait(arch_rwlock_t *lp);
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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if (!arch_read_trylock_once(rw))
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_raw_read_lock_wait(rw);
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned int old;
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do {
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old = ACCESS_ONCE(rw->lock);
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} while (!_raw_compare_and_swap(&rw->lock, old, old - 1));
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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if (!arch_write_trylock_once(rw))
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_raw_write_lock_wait(rw);
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rw->owner = SPINLOCK_LOCKVAL;
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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typecheck(unsigned int, rw->lock);
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rw->owner = 0;
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asm volatile(
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"st %1,%0\n"
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: "+Q" (rw->lock)
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: "d" (0)
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: "cc", "memory");
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}
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#endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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if (!arch_read_trylock_once(rw))
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return _raw_read_trylock_retry(rw);
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return 1;
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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if (!arch_write_trylock_once(rw) && !_raw_write_trylock_retry(rw))
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return 0;
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rw->owner = SPINLOCK_LOCKVAL;
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return 1;
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}
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static inline void arch_read_relax(arch_rwlock_t *rw)
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{
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arch_lock_relax(rw->owner);
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}
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static inline void arch_write_relax(arch_rwlock_t *rw)
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{
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arch_lock_relax(rw->owner);
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}
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#endif /* __ASM_SPINLOCK_H */
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