167 lines
4.2 KiB
C
167 lines
4.2 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* These routines make two important assumptions:
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*
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* 1. atomic_t is really an int and can be freely cast back and forth
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* (validated in __init_atomic_per_cpu).
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*
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* 2. userspace uses sys_cmpxchg() for all atomic operations, thus using
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* the same locking convention that all the kernel atomic routines use.
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*/
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#ifndef _ASM_TILE_FUTEX_H
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#define _ASM_TILE_FUTEX_H
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#ifndef __ASSEMBLY__
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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#include <linux/errno.h>
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#include <asm/atomic.h>
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/*
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* Support macros for futex operations. Do not use these macros directly.
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* They assume "ret", "val", "oparg", and "uaddr" in the lexical context.
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* __futex_cmpxchg() additionally assumes "oldval".
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*/
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#ifdef __tilegx__
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#define __futex_asm(OP) \
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asm("1: {" #OP " %1, %3, %4; movei %0, 0 }\n" \
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".pushsection .fixup,\"ax\"\n" \
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"0: { movei %0, %5; j 9f }\n" \
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".section __ex_table,\"a\"\n" \
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".align 8\n" \
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".quad 1b, 0b\n" \
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".popsection\n" \
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"9:" \
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: "=r" (ret), "=r" (val), "+m" (*(uaddr)) \
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: "r" (uaddr), "r" (oparg), "i" (-EFAULT))
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#define __futex_set() __futex_asm(exch4)
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#define __futex_add() __futex_asm(fetchadd4)
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#define __futex_or() __futex_asm(fetchor4)
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#define __futex_andn() ({ oparg = ~oparg; __futex_asm(fetchand4); })
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#define __futex_cmpxchg() \
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({ __insn_mtspr(SPR_CMPEXCH_VALUE, oldval); __futex_asm(cmpexch4); })
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#define __futex_xor() \
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({ \
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u32 oldval, n = oparg; \
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if ((ret = __get_user(oldval, uaddr)) == 0) { \
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do { \
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oparg = oldval ^ n; \
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__futex_cmpxchg(); \
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} while (ret == 0 && oldval != val); \
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} \
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})
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/* No need to prefetch, since the atomic ops go to the home cache anyway. */
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#define __futex_prolog()
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#else
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#define __futex_call(FN) \
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{ \
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struct __get_user gu = FN((u32 __force *)uaddr, lock, oparg); \
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val = gu.val; \
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ret = gu.err; \
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}
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#define __futex_set() __futex_call(__atomic32_xchg)
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#define __futex_add() __futex_call(__atomic32_xchg_add)
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#define __futex_or() __futex_call(__atomic32_fetch_or)
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#define __futex_andn() __futex_call(__atomic32_fetch_andn)
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#define __futex_xor() __futex_call(__atomic32_fetch_xor)
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#define __futex_cmpxchg() \
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{ \
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struct __get_user gu = __atomic32_cmpxchg((u32 __force *)uaddr, \
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lock, oldval, oparg); \
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val = gu.val; \
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ret = gu.err; \
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}
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/*
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* Find the lock pointer for the atomic calls to use, and issue a
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* prefetch to the user address to bring it into cache. Similar to
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* __atomic_setup(), but we can't do a read into the L1 since it might
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* fault; instead we do a prefetch into the L2.
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*/
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#define __futex_prolog() \
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int *lock; \
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__insn_prefetch(uaddr); \
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lock = __atomic_hashed_lock((int __force *)uaddr)
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#endif
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static inline int arch_futex_atomic_op_inuser(int op, u32 oparg, int *oval,
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u32 __user *uaddr)
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{
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int uninitialized_var(val), ret;
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__futex_prolog();
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/* The 32-bit futex code makes this assumption, so validate it here. */
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BUILD_BUG_ON(sizeof(atomic_t) != sizeof(int));
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pagefault_disable();
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switch (op) {
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case FUTEX_OP_SET:
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__futex_set();
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break;
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case FUTEX_OP_ADD:
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__futex_add();
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break;
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case FUTEX_OP_OR:
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__futex_or();
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break;
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case FUTEX_OP_ANDN:
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__futex_andn();
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break;
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case FUTEX_OP_XOR:
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__futex_xor();
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break;
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default:
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ret = -ENOSYS;
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break;
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}
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pagefault_enable();
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if (!ret)
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*oval = val;
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return ret;
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}
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static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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u32 oldval, u32 oparg)
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{
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int ret, val;
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__futex_prolog();
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
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return -EFAULT;
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__futex_cmpxchg();
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*uval = val;
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return ret;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_TILE_FUTEX_H */
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