1573 lines
45 KiB
ArmAsm
1573 lines
45 KiB
ArmAsm
/*
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* linux/arch/x86_64/entry.S
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*
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* Copyright (C) 1991, 1992 Linus Torvalds
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* Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
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* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
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*
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* entry.S contains the system-call and fault low-level handling routines.
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*
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* Some of this is documented in Documentation/x86/entry_64.txt
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*
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* A note on terminology:
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* - iret frame: Architecture defined interrupt frame from SS to RIP
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* at the top of the kernel process stack.
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*
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* Some macro usage:
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* - ENTRY/END: Define functions in the symbol table.
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* - TRACE_IRQ_*: Trace hardirq state for lock debugging.
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* - idtentry: Define exception entry points.
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*/
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/cache.h>
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#include <asm/errno.h>
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#include "calling.h"
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#include <asm/asm-offsets.h>
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#include <asm/msr.h>
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#include <asm/unistd.h>
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#include <asm/thread_info.h>
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#include <asm/hw_irq.h>
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#include <asm/page_types.h>
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#include <asm/irqflags.h>
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#include <asm/paravirt.h>
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#include <asm/percpu.h>
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#include <asm/asm.h>
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#include <asm/smap.h>
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#include <asm/pgtable_types.h>
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#include <asm/export.h>
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#include <asm/kaiser.h>
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#include <asm/nospec-branch.h>
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#include <linux/err.h>
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/* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */
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#include <linux/elf-em.h>
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#define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
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#define __AUDIT_ARCH_64BIT 0x80000000
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#define __AUDIT_ARCH_LE 0x40000000
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.code64
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.section .entry.text, "ax"
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#ifdef CONFIG_PARAVIRT
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ENTRY(native_usergs_sysret64)
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swapgs
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sysretq
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ENDPROC(native_usergs_sysret64)
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#endif /* CONFIG_PARAVIRT */
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.macro TRACE_IRQS_IRETQ
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#ifdef CONFIG_TRACE_IRQFLAGS
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btl $9, EFLAGS(%rsp) /* interrupts off? */
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jnc 1f
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TRACE_IRQS_ON
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1:
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#endif
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.endm
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/*
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* When dynamic function tracer is enabled it will add a breakpoint
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* to all locations that it is about to modify, sync CPUs, update
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* all the code, sync CPUs, then remove the breakpoints. In this time
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* if lockdep is enabled, it might jump back into the debug handler
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* outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
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*
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* We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
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* make sure the stack pointer does not get reset back to the top
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* of the debug stack, and instead just reuses the current stack.
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*/
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#if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
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.macro TRACE_IRQS_OFF_DEBUG
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call debug_stack_set_zero
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TRACE_IRQS_OFF
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call debug_stack_reset
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.endm
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.macro TRACE_IRQS_ON_DEBUG
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call debug_stack_set_zero
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TRACE_IRQS_ON
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call debug_stack_reset
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.endm
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.macro TRACE_IRQS_IRETQ_DEBUG
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btl $9, EFLAGS(%rsp) /* interrupts off? */
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jnc 1f
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TRACE_IRQS_ON_DEBUG
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1:
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.endm
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#else
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# define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
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# define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
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# define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
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#endif
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/*
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* 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
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*
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* This is the only entry point used for 64-bit system calls. The
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* hardware interface is reasonably well designed and the register to
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* argument mapping Linux uses fits well with the registers that are
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* available when SYSCALL is used.
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*
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* SYSCALL instructions can be found inlined in libc implementations as
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* well as some other programs and libraries. There are also a handful
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* of SYSCALL instructions in the vDSO used, for example, as a
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* clock_gettimeofday fallback.
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*
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* 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
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* then loads new ss, cs, and rip from previously programmed MSRs.
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* rflags gets masked by a value from another MSR (so CLD and CLAC
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* are not needed). SYSCALL does not save anything on the stack
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* and does not change rsp.
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*
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* Registers on entry:
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* rax system call number
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* rcx return address
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* r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
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* rdi arg0
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* rsi arg1
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* rdx arg2
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* r10 arg3 (needs to be moved to rcx to conform to C ABI)
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* r8 arg4
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* r9 arg5
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* (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
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*
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* Only called from user space.
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*
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* When user can change pt_regs->foo always force IRET. That is because
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* it deals with uncanonical addresses better. SYSRET has trouble
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* with them due to bugs in both AMD and Intel CPUs.
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*/
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ENTRY(entry_SYSCALL_64)
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/*
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* Interrupts are off on entry.
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* We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
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* it is too small to ever cause noticeable irq latency.
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*/
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SWAPGS_UNSAFE_STACK
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SWITCH_KERNEL_CR3_NO_STACK
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/*
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* A hypervisor implementation might want to use a label
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* after the swapgs, so that it can do the swapgs
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* for the guest and jump here on syscall.
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*/
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GLOBAL(entry_SYSCALL_64_after_swapgs)
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movq %rsp, PER_CPU_VAR(rsp_scratch)
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movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
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TRACE_IRQS_OFF
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/* Construct struct pt_regs on stack */
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pushq $__USER_DS /* pt_regs->ss */
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pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
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pushq %r11 /* pt_regs->flags */
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pushq $__USER_CS /* pt_regs->cs */
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pushq %rcx /* pt_regs->ip */
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pushq %rax /* pt_regs->orig_ax */
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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pushq %rdx /* pt_regs->dx */
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pushq %rcx /* pt_regs->cx */
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pushq $-ENOSYS /* pt_regs->ax */
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pushq %r8 /* pt_regs->r8 */
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pushq %r9 /* pt_regs->r9 */
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pushq %r10 /* pt_regs->r10 */
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/*
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* Clear extra registers that a speculation attack might
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* otherwise want to exploit. Interleave XOR with PUSH
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* for better uop scheduling:
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*/
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xorq %r10, %r10 /* nospec r10 */
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pushq %r11 /* pt_regs->r11 */
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xorq %r11, %r11 /* nospec r11 */
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pushq %rbx /* pt_regs->rbx */
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xorl %ebx, %ebx /* nospec rbx */
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pushq %rbp /* pt_regs->rbp */
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xorl %ebp, %ebp /* nospec rbp */
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pushq %r12 /* pt_regs->r12 */
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xorq %r12, %r12 /* nospec r12 */
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pushq %r13 /* pt_regs->r13 */
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xorq %r13, %r13 /* nospec r13 */
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pushq %r14 /* pt_regs->r14 */
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xorq %r14, %r14 /* nospec r14 */
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pushq %r15 /* pt_regs->r15 */
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xorq %r15, %r15 /* nospec r15 */
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/* IRQs are off. */
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movq %rsp, %rdi
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call do_syscall_64 /* returns with IRQs disabled */
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RESTORE_EXTRA_REGS
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TRACE_IRQS_IRETQ /* we're about to change IF */
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/*
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* Try to use SYSRET instead of IRET if we're returning to
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* a completely clean 64-bit userspace context.
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*/
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movq RCX(%rsp), %rcx
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movq RIP(%rsp), %r11
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cmpq %rcx, %r11 /* RCX == RIP */
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jne opportunistic_sysret_failed
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/*
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* On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
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* in kernel space. This essentially lets the user take over
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* the kernel, since userspace controls RSP.
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*
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* If width of "canonical tail" ever becomes variable, this will need
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* to be updated to remain correct on both old and new CPUs.
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*/
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.ifne __VIRTUAL_MASK_SHIFT - 47
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.error "virtual address width changed -- SYSRET checks need update"
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.endif
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/* Change top 16 bits to be the sign-extension of 47th bit */
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shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
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sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
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/* If this changed %rcx, it was not canonical */
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cmpq %rcx, %r11
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jne opportunistic_sysret_failed
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cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
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jne opportunistic_sysret_failed
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movq R11(%rsp), %r11
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cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
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jne opportunistic_sysret_failed
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/*
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* SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
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* restore RF properly. If the slowpath sets it for whatever reason, we
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* need to restore it correctly.
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*
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* SYSRET can restore TF, but unlike IRET, restoring TF results in a
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* trap from userspace immediately after SYSRET. This would cause an
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* infinite loop whenever #DB happens with register state that satisfies
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* the opportunistic SYSRET conditions. For example, single-stepping
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* this user code:
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*
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* movq $stuck_here, %rcx
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* pushfq
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* popq %r11
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* stuck_here:
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*
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* would never get past 'stuck_here'.
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*/
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testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
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jnz opportunistic_sysret_failed
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/* nothing to check for RSP */
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cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
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jne opportunistic_sysret_failed
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/*
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* We win! This label is here just for ease of understanding
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* perf profiles. Nothing jumps here.
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*/
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syscall_return_via_sysret:
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/* rcx and r11 are already restored (see code above) */
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RESTORE_C_REGS_EXCEPT_RCX_R11
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/*
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* This opens a window where we have a user CR3, but are
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* running in the kernel. This makes using the CS
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* register useless for telling whether or not we need to
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* switch CR3 in NMIs. Normal interrupts are OK because
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* they are off here.
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*/
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SWITCH_USER_CR3
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movq RSP(%rsp), %rsp
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USERGS_SYSRET64
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opportunistic_sysret_failed:
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/*
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* This opens a window where we have a user CR3, but are
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* running in the kernel. This makes using the CS
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* register useless for telling whether or not we need to
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* switch CR3 in NMIs. Normal interrupts are OK because
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* they are off here.
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*/
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SWITCH_USER_CR3
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SWAPGS
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jmp restore_c_regs_and_iret
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END(entry_SYSCALL_64)
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/*
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* %rdi: prev task
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* %rsi: next task
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*/
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ENTRY(__switch_to_asm)
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/*
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* Save callee-saved registers
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* This must match the order in inactive_task_frame
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*/
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pushq %rbp
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pushq %rbx
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pushq %r12
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pushq %r13
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pushq %r14
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pushq %r15
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pushfq
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/* switch stack */
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movq %rsp, TASK_threadsp(%rdi)
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movq TASK_threadsp(%rsi), %rsp
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#ifdef CONFIG_CC_STACKPROTECTOR
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movq TASK_stack_canary(%rsi), %rbx
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movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
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#endif
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#ifdef CONFIG_RETPOLINE
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/*
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* When switching from a shallower to a deeper call stack
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* the RSB may either underflow or use entries populated
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* with userspace addresses. On CPUs where those concerns
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* exist, overwrite the RSB with entries which capture
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* speculative execution to prevent attack.
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*/
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FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
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#endif
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/* restore callee-saved registers */
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popfq
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popq %r15
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popq %r14
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popq %r13
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popq %r12
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popq %rbx
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popq %rbp
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jmp __switch_to
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END(__switch_to_asm)
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/*
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* A newly forked process directly context switches into this address.
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*
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* rax: prev task we switched from
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* rbx: kernel thread func (NULL for user thread)
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* r12: kernel thread arg
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*/
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ENTRY(ret_from_fork)
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movq %rax, %rdi
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call schedule_tail /* rdi: 'prev' task parameter */
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testq %rbx, %rbx /* from kernel_thread? */
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jnz 1f /* kernel threads are uncommon */
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2:
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movq %rsp, %rdi
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call syscall_return_slowpath /* returns with IRQs disabled */
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TRACE_IRQS_ON /* user mode is traced as IRQS on */
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SWITCH_USER_CR3
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SWAPGS
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jmp restore_regs_and_iret
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1:
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/* kernel thread */
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movq %r12, %rdi
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CALL_NOSPEC %rbx
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/*
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* A kernel thread is allowed to return here after successfully
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* calling do_execve(). Exit to userspace to complete the execve()
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* syscall.
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*/
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movq $0, RAX(%rsp)
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jmp 2b
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END(ret_from_fork)
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/*
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* Build the entry stubs with some assembler magic.
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* We pack 1 stub into every 8-byte block.
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*/
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.align 8
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ENTRY(irq_entries_start)
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vector=FIRST_EXTERNAL_VECTOR
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.rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
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pushq $(~vector+0x80) /* Note: always in signed byte range */
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vector=vector+1
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jmp common_interrupt
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.align 8
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.endr
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END(irq_entries_start)
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/*
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* Interrupt entry/exit.
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*
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* Interrupt entry points save only callee clobbered registers in fast path.
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*
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* Entry runs with interrupts off.
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*/
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/* 0(%rsp): ~(interrupt number) */
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.macro interrupt func
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cld
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ALLOC_PT_GPREGS_ON_STACK
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SAVE_C_REGS
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SAVE_EXTRA_REGS
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testb $3, CS(%rsp)
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jz 1f
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/*
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* IRQ from user mode. Switch to kernel gsbase and inform context
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* tracking that we're in kernel mode.
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*/
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_KERNEL_CR3
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/*
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* We need to tell lockdep that IRQs are off. We can't do this until
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* we fix gsbase, and we should do it before enter_from_user_mode
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* (which can take locks). Since TRACE_IRQS_OFF idempotent,
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* the simplest way to handle it is to just call it twice if
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* we enter from user mode. There's no reason to optimize this since
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* TRACE_IRQS_OFF is a no-op if lockdep is off.
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*/
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TRACE_IRQS_OFF
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CALL_enter_from_user_mode
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jmp 2f
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1:
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FENCE_SWAPGS_KERNEL_ENTRY
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2:
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/*
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* Save previous stack pointer, optionally switch to interrupt stack.
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* irq_count is used to check if a CPU is already on an interrupt stack
|
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* or not. While this is essentially redundant with preempt_count it is
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* a little cheaper to use a separate counter in the PDA (short of
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* moving irq_enter into assembly, which would be too much work)
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*/
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movq %rsp, %rdi
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incl PER_CPU_VAR(irq_count)
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cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp
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pushq %rdi
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/* We entered an interrupt context - irqs are off: */
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TRACE_IRQS_OFF
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call \func /* rdi points to pt_regs */
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.endm
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/*
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* The interrupt stubs push (~vector+0x80) onto the stack and
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* then jump to common_interrupt.
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*/
|
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.p2align CONFIG_X86_L1_CACHE_SHIFT
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common_interrupt:
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ASM_CLAC
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addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
|
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interrupt do_IRQ
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/* 0(%rsp): old RSP */
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ret_from_intr:
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DISABLE_INTERRUPTS(CLBR_NONE)
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TRACE_IRQS_OFF
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decl PER_CPU_VAR(irq_count)
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/* Restore saved previous stack */
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popq %rsp
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testb $3, CS(%rsp)
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jz retint_kernel
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/* Interrupt came from user space */
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GLOBAL(retint_user)
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mov %rsp,%rdi
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call prepare_exit_to_usermode
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TRACE_IRQS_IRETQ
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SWITCH_USER_CR3
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SWAPGS
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jmp restore_regs_and_iret
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|
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/* Returning to kernel space */
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retint_kernel:
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#ifdef CONFIG_PREEMPT
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/* Interrupts are off */
|
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/* Check if we need preemption */
|
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btl $9, EFLAGS(%rsp) /* were interrupts off? */
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jnc 1f
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0: cmpl $0, PER_CPU_VAR(__preempt_count)
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jnz 1f
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call preempt_schedule_irq
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jmp 0b
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1:
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#endif
|
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/*
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* The iretq could re-enable interrupts:
|
|
*/
|
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TRACE_IRQS_IRETQ
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|
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/*
|
|
* At this label, code paths which return to kernel and to user,
|
|
* which come from interrupts/exception and from syscalls, merge.
|
|
*/
|
|
GLOBAL(restore_regs_and_iret)
|
|
RESTORE_EXTRA_REGS
|
|
restore_c_regs_and_iret:
|
|
RESTORE_C_REGS
|
|
REMOVE_PT_GPREGS_FROM_STACK 8
|
|
INTERRUPT_RETURN
|
|
|
|
ENTRY(native_iret)
|
|
/*
|
|
* Are we returning to a stack segment from the LDT? Note: in
|
|
* 64-bit mode SS:RSP on the exception stack is always valid.
|
|
*/
|
|
#ifdef CONFIG_X86_ESPFIX64
|
|
testb $4, (SS-RIP)(%rsp)
|
|
jnz native_irq_return_ldt
|
|
#endif
|
|
|
|
.global native_irq_return_iret
|
|
native_irq_return_iret:
|
|
/*
|
|
* This may fault. Non-paranoid faults on return to userspace are
|
|
* handled by fixup_bad_iret. These include #SS, #GP, and #NP.
|
|
* Double-faults due to espfix64 are handled in do_double_fault.
|
|
* Other faults here are fatal.
|
|
*/
|
|
iretq
|
|
|
|
#ifdef CONFIG_X86_ESPFIX64
|
|
native_irq_return_ldt:
|
|
/*
|
|
* We are running with user GSBASE. All GPRs contain their user
|
|
* values. We have a percpu ESPFIX stack that is eight slots
|
|
* long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
|
|
* of the ESPFIX stack.
|
|
*
|
|
* We clobber RAX and RDI in this code. We stash RDI on the
|
|
* normal stack and RAX on the ESPFIX stack.
|
|
*
|
|
* The ESPFIX stack layout we set up looks like this:
|
|
*
|
|
* --- top of ESPFIX stack ---
|
|
* SS
|
|
* RSP
|
|
* RFLAGS
|
|
* CS
|
|
* RIP <-- RSP points here when we're done
|
|
* RAX <-- espfix_waddr points here
|
|
* --- bottom of ESPFIX stack ---
|
|
*/
|
|
|
|
pushq %rdi /* Stash user RDI */
|
|
SWAPGS
|
|
SWITCH_KERNEL_CR3
|
|
movq PER_CPU_VAR(espfix_waddr), %rdi
|
|
movq %rax, (0*8)(%rdi) /* user RAX */
|
|
movq (1*8)(%rsp), %rax /* user RIP */
|
|
movq %rax, (1*8)(%rdi)
|
|
movq (2*8)(%rsp), %rax /* user CS */
|
|
movq %rax, (2*8)(%rdi)
|
|
movq (3*8)(%rsp), %rax /* user RFLAGS */
|
|
movq %rax, (3*8)(%rdi)
|
|
movq (5*8)(%rsp), %rax /* user SS */
|
|
movq %rax, (5*8)(%rdi)
|
|
movq (4*8)(%rsp), %rax /* user RSP */
|
|
movq %rax, (4*8)(%rdi)
|
|
/* Now RAX == RSP. */
|
|
|
|
andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
|
|
popq %rdi /* Restore user RDI */
|
|
|
|
/*
|
|
* espfix_stack[31:16] == 0. The page tables are set up such that
|
|
* (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
|
|
* espfix_waddr for any X. That is, there are 65536 RO aliases of
|
|
* the same page. Set up RSP so that RSP[31:16] contains the
|
|
* respective 16 bits of the /userspace/ RSP and RSP nonetheless
|
|
* still points to an RO alias of the ESPFIX stack.
|
|
*/
|
|
orq PER_CPU_VAR(espfix_stack), %rax
|
|
SWITCH_USER_CR3
|
|
SWAPGS
|
|
movq %rax, %rsp
|
|
|
|
/*
|
|
* At this point, we cannot write to the stack any more, but we can
|
|
* still read.
|
|
*/
|
|
popq %rax /* Restore user RAX */
|
|
|
|
/*
|
|
* RSP now points to an ordinary IRET frame, except that the page
|
|
* is read-only and RSP[31:16] are preloaded with the userspace
|
|
* values. We can now IRET back to userspace.
|
|
*/
|
|
jmp native_irq_return_iret
|
|
#endif
|
|
END(common_interrupt)
|
|
|
|
/*
|
|
* APIC interrupts.
|
|
*/
|
|
.macro apicinterrupt3 num sym do_sym
|
|
ENTRY(\sym)
|
|
ASM_CLAC
|
|
pushq $~(\num)
|
|
.Lcommon_\sym:
|
|
interrupt \do_sym
|
|
jmp ret_from_intr
|
|
END(\sym)
|
|
.endm
|
|
|
|
#ifdef CONFIG_TRACING
|
|
#define trace(sym) trace_##sym
|
|
#define smp_trace(sym) smp_trace_##sym
|
|
|
|
.macro trace_apicinterrupt num sym
|
|
apicinterrupt3 \num trace(\sym) smp_trace(\sym)
|
|
.endm
|
|
#else
|
|
.macro trace_apicinterrupt num sym do_sym
|
|
.endm
|
|
#endif
|
|
|
|
/* Make sure APIC interrupt handlers end up in the irqentry section: */
|
|
#define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
|
|
#define POP_SECTION_IRQENTRY .popsection
|
|
|
|
.macro apicinterrupt num sym do_sym
|
|
PUSH_SECTION_IRQENTRY
|
|
apicinterrupt3 \num \sym \do_sym
|
|
trace_apicinterrupt \num \sym
|
|
POP_SECTION_IRQENTRY
|
|
.endm
|
|
|
|
#ifdef CONFIG_SMP
|
|
apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
|
|
apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86_UV
|
|
apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
|
|
#endif
|
|
|
|
apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
|
|
apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
|
|
|
|
#ifdef CONFIG_HAVE_KVM
|
|
apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
|
|
apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86_MCE_THRESHOLD
|
|
apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86_MCE_AMD
|
|
apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86_THERMAL_VECTOR
|
|
apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMP
|
|
apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
|
|
apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
|
|
apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
|
|
#endif
|
|
|
|
apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
|
|
apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
|
|
|
|
#ifdef CONFIG_IRQ_WORK
|
|
apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
|
|
#endif
|
|
|
|
/*
|
|
* Exception entry points.
|
|
*/
|
|
#define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8)
|
|
|
|
.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
|
|
ENTRY(\sym)
|
|
/* Sanity check */
|
|
.if \shift_ist != -1 && \paranoid == 0
|
|
.error "using shift_ist requires paranoid=1"
|
|
.endif
|
|
|
|
ASM_CLAC
|
|
PARAVIRT_ADJUST_EXCEPTION_FRAME
|
|
|
|
.ifeq \has_error_code
|
|
pushq $-1 /* ORIG_RAX: no syscall to restart */
|
|
.endif
|
|
|
|
ALLOC_PT_GPREGS_ON_STACK
|
|
|
|
.if \paranoid
|
|
.if \paranoid == 1
|
|
testb $3, CS(%rsp) /* If coming from userspace, switch stacks */
|
|
jnz 1f
|
|
.endif
|
|
call paranoid_entry
|
|
.else
|
|
call error_entry
|
|
.endif
|
|
/* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
|
|
|
|
.if \paranoid
|
|
.if \shift_ist != -1
|
|
TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
|
|
.else
|
|
TRACE_IRQS_OFF
|
|
.endif
|
|
.endif
|
|
|
|
movq %rsp, %rdi /* pt_regs pointer */
|
|
|
|
.if \has_error_code
|
|
movq ORIG_RAX(%rsp), %rsi /* get error code */
|
|
movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
|
|
.else
|
|
xorl %esi, %esi /* no error code */
|
|
.endif
|
|
|
|
.if \shift_ist != -1
|
|
subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
|
|
.endif
|
|
|
|
call \do_sym
|
|
|
|
.if \shift_ist != -1
|
|
addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
|
|
.endif
|
|
|
|
/* these procedures expect "no swapgs" flag in ebx */
|
|
.if \paranoid
|
|
jmp paranoid_exit
|
|
.else
|
|
jmp error_exit
|
|
.endif
|
|
|
|
.if \paranoid == 1
|
|
/*
|
|
* Paranoid entry from userspace. Switch stacks and treat it
|
|
* as a normal entry. This means that paranoid handlers
|
|
* run in real process context if user_mode(regs).
|
|
*/
|
|
1:
|
|
call error_entry
|
|
|
|
|
|
movq %rsp, %rdi /* pt_regs pointer */
|
|
call sync_regs
|
|
movq %rax, %rsp /* switch stack */
|
|
|
|
movq %rsp, %rdi /* pt_regs pointer */
|
|
|
|
.if \has_error_code
|
|
movq ORIG_RAX(%rsp), %rsi /* get error code */
|
|
movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
|
|
.else
|
|
xorl %esi, %esi /* no error code */
|
|
.endif
|
|
|
|
call \do_sym
|
|
|
|
jmp error_exit
|
|
.endif
|
|
END(\sym)
|
|
.endm
|
|
|
|
#ifdef CONFIG_TRACING
|
|
.macro trace_idtentry sym do_sym has_error_code:req
|
|
idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code
|
|
idtentry \sym \do_sym has_error_code=\has_error_code
|
|
.endm
|
|
#else
|
|
.macro trace_idtentry sym do_sym has_error_code:req
|
|
idtentry \sym \do_sym has_error_code=\has_error_code
|
|
.endm
|
|
#endif
|
|
|
|
idtentry divide_error do_divide_error has_error_code=0
|
|
idtentry overflow do_overflow has_error_code=0
|
|
idtentry bounds do_bounds has_error_code=0
|
|
idtentry invalid_op do_invalid_op has_error_code=0
|
|
idtentry device_not_available do_device_not_available has_error_code=0
|
|
idtentry double_fault do_double_fault has_error_code=1 paranoid=2
|
|
idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
|
|
idtentry invalid_TSS do_invalid_TSS has_error_code=1
|
|
idtentry segment_not_present do_segment_not_present has_error_code=1
|
|
idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
|
|
idtentry coprocessor_error do_coprocessor_error has_error_code=0
|
|
idtentry alignment_check do_alignment_check has_error_code=1
|
|
idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
|
|
|
|
|
|
/*
|
|
* Reload gs selector with exception handling
|
|
* edi: new selector
|
|
*/
|
|
ENTRY(native_load_gs_index)
|
|
pushfq
|
|
DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
|
|
SWAPGS
|
|
.Lgs_change:
|
|
movl %edi, %gs
|
|
2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
|
|
SWAPGS
|
|
popfq
|
|
ret
|
|
END(native_load_gs_index)
|
|
EXPORT_SYMBOL(native_load_gs_index)
|
|
|
|
_ASM_EXTABLE(.Lgs_change, bad_gs)
|
|
.section .fixup, "ax"
|
|
/* running with kernelgs */
|
|
bad_gs:
|
|
SWAPGS /* switch back to user gs */
|
|
.macro ZAP_GS
|
|
/* This can't be a string because the preprocessor needs to see it. */
|
|
movl $__USER_DS, %eax
|
|
movl %eax, %gs
|
|
.endm
|
|
ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
|
|
xorl %eax, %eax
|
|
movl %eax, %gs
|
|
jmp 2b
|
|
.previous
|
|
|
|
/* Call softirq on interrupt stack. Interrupts are off. */
|
|
ENTRY(do_softirq_own_stack)
|
|
pushq %rbp
|
|
mov %rsp, %rbp
|
|
incl PER_CPU_VAR(irq_count)
|
|
cmove PER_CPU_VAR(irq_stack_ptr), %rsp
|
|
push %rbp /* frame pointer backlink */
|
|
call __do_softirq
|
|
leaveq
|
|
decl PER_CPU_VAR(irq_count)
|
|
ret
|
|
END(do_softirq_own_stack)
|
|
|
|
#ifdef CONFIG_XEN
|
|
idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0
|
|
|
|
/*
|
|
* A note on the "critical region" in our callback handler.
|
|
* We want to avoid stacking callback handlers due to events occurring
|
|
* during handling of the last event. To do this, we keep events disabled
|
|
* until we've done all processing. HOWEVER, we must enable events before
|
|
* popping the stack frame (can't be done atomically) and so it would still
|
|
* be possible to get enough handler activations to overflow the stack.
|
|
* Although unlikely, bugs of that kind are hard to track down, so we'd
|
|
* like to avoid the possibility.
|
|
* So, on entry to the handler we detect whether we interrupted an
|
|
* existing activation in its critical region -- if so, we pop the current
|
|
* activation and restart the handler using the previous one.
|
|
*/
|
|
ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
|
|
|
|
/*
|
|
* Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
|
|
* see the correct pointer to the pt_regs
|
|
*/
|
|
movq %rdi, %rsp /* we don't return, adjust the stack frame */
|
|
11: incl PER_CPU_VAR(irq_count)
|
|
movq %rsp, %rbp
|
|
cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp
|
|
pushq %rbp /* frame pointer backlink */
|
|
call xen_evtchn_do_upcall
|
|
popq %rsp
|
|
decl PER_CPU_VAR(irq_count)
|
|
#ifndef CONFIG_PREEMPT
|
|
call xen_maybe_preempt_hcall
|
|
#endif
|
|
jmp error_exit
|
|
END(xen_do_hypervisor_callback)
|
|
|
|
/*
|
|
* Hypervisor uses this for application faults while it executes.
|
|
* We get here for two reasons:
|
|
* 1. Fault while reloading DS, ES, FS or GS
|
|
* 2. Fault while executing IRET
|
|
* Category 1 we do not need to fix up as Xen has already reloaded all segment
|
|
* registers that could be reloaded and zeroed the others.
|
|
* Category 2 we fix up by killing the current process. We cannot use the
|
|
* normal Linux return path in this case because if we use the IRET hypercall
|
|
* to pop the stack frame we end up in an infinite loop of failsafe callbacks.
|
|
* We distinguish between categories by comparing each saved segment register
|
|
* with its current contents: any discrepancy means we in category 1.
|
|
*/
|
|
ENTRY(xen_failsafe_callback)
|
|
movl %ds, %ecx
|
|
cmpw %cx, 0x10(%rsp)
|
|
jne 1f
|
|
movl %es, %ecx
|
|
cmpw %cx, 0x18(%rsp)
|
|
jne 1f
|
|
movl %fs, %ecx
|
|
cmpw %cx, 0x20(%rsp)
|
|
jne 1f
|
|
movl %gs, %ecx
|
|
cmpw %cx, 0x28(%rsp)
|
|
jne 1f
|
|
/* All segments match their saved values => Category 2 (Bad IRET). */
|
|
movq (%rsp), %rcx
|
|
movq 8(%rsp), %r11
|
|
addq $0x30, %rsp
|
|
pushq $0 /* RIP */
|
|
pushq %r11
|
|
pushq %rcx
|
|
jmp general_protection
|
|
1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
|
|
movq (%rsp), %rcx
|
|
movq 8(%rsp), %r11
|
|
addq $0x30, %rsp
|
|
pushq $-1 /* orig_ax = -1 => not a system call */
|
|
ALLOC_PT_GPREGS_ON_STACK
|
|
SAVE_C_REGS
|
|
SAVE_EXTRA_REGS
|
|
jmp error_exit
|
|
END(xen_failsafe_callback)
|
|
|
|
apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
|
|
xen_hvm_callback_vector xen_evtchn_do_upcall
|
|
|
|
#endif /* CONFIG_XEN */
|
|
|
|
#if IS_ENABLED(CONFIG_HYPERV)
|
|
apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
|
|
hyperv_callback_vector hyperv_vector_handler
|
|
#endif /* CONFIG_HYPERV */
|
|
|
|
idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
|
|
idtentry int3 do_int3 has_error_code=0
|
|
idtentry stack_segment do_stack_segment has_error_code=1
|
|
|
|
#ifdef CONFIG_XEN
|
|
idtentry xen_debug do_debug has_error_code=0
|
|
idtentry xen_int3 do_int3 has_error_code=0
|
|
idtentry xen_stack_segment do_stack_segment has_error_code=1
|
|
#endif
|
|
|
|
idtentry general_protection do_general_protection has_error_code=1
|
|
trace_idtentry page_fault do_page_fault has_error_code=1
|
|
|
|
#ifdef CONFIG_KVM_GUEST
|
|
idtentry async_page_fault do_async_page_fault has_error_code=1
|
|
#endif
|
|
|
|
#ifdef CONFIG_X86_MCE
|
|
idtentry machine_check do_mce has_error_code=0 paranoid=1
|
|
#endif
|
|
|
|
/*
|
|
* Save all registers in pt_regs, and switch gs if needed.
|
|
* Use slow, but surefire "are we in kernel?" check.
|
|
*
|
|
* Return: ebx=0: needs swapgs but not SWITCH_USER_CR3 in paranoid_exit
|
|
* ebx=1: needs neither swapgs nor SWITCH_USER_CR3 in paranoid_exit
|
|
* ebx=2: needs both swapgs and SWITCH_USER_CR3 in paranoid_exit
|
|
* ebx=3: needs SWITCH_USER_CR3 but not swapgs in paranoid_exit
|
|
*/
|
|
ENTRY(paranoid_entry)
|
|
cld
|
|
SAVE_C_REGS 8
|
|
SAVE_EXTRA_REGS 8
|
|
movl $1, %ebx
|
|
movl $MSR_GS_BASE, %ecx
|
|
rdmsr
|
|
testl %edx, %edx
|
|
js 1f /* negative -> in kernel */
|
|
SWAPGS
|
|
xorl %ebx, %ebx
|
|
1:
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
/*
|
|
* We might have come in between a swapgs and a SWITCH_KERNEL_CR3
|
|
* on entry, or between a SWITCH_USER_CR3 and a swapgs on exit.
|
|
* Do a conditional SWITCH_KERNEL_CR3: this could safely be done
|
|
* unconditionally, but we need to find out whether the reverse
|
|
* should be done on return (conveyed to paranoid_exit in %ebx).
|
|
*/
|
|
ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
|
|
testl $KAISER_SHADOW_PGD_OFFSET, %eax
|
|
jz 2f
|
|
orl $2, %ebx
|
|
andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
|
|
/* If PCID enabled, set X86_CR3_PCID_NOFLUSH_BIT */
|
|
ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
|
|
movq %rax, %cr3
|
|
2:
|
|
#endif
|
|
/*
|
|
* The above doesn't do an unconditional CR3 write, even in the PTI
|
|
* case. So do an lfence to prevent GS speculation, regardless of
|
|
* whether PTI is enabled.
|
|
*/
|
|
FENCE_SWAPGS_KERNEL_ENTRY
|
|
|
|
ret
|
|
END(paranoid_entry)
|
|
|
|
/*
|
|
* "Paranoid" exit path from exception stack. This is invoked
|
|
* only on return from non-NMI IST interrupts that came
|
|
* from kernel space.
|
|
*
|
|
* We may be returning to very strange contexts (e.g. very early
|
|
* in syscall entry), so checking for preemption here would
|
|
* be complicated. Fortunately, we there's no good reason
|
|
* to try to handle preemption here.
|
|
*
|
|
* On entry: ebx=0: needs swapgs but not SWITCH_USER_CR3
|
|
* ebx=1: needs neither swapgs nor SWITCH_USER_CR3
|
|
* ebx=2: needs both swapgs and SWITCH_USER_CR3
|
|
* ebx=3: needs SWITCH_USER_CR3 but not swapgs
|
|
*/
|
|
ENTRY(paranoid_exit)
|
|
DISABLE_INTERRUPTS(CLBR_NONE)
|
|
TRACE_IRQS_OFF_DEBUG
|
|
TRACE_IRQS_IRETQ_DEBUG
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
/* No ALTERNATIVE for X86_FEATURE_KAISER: paranoid_entry sets %ebx */
|
|
testl $2, %ebx /* SWITCH_USER_CR3 needed? */
|
|
jz paranoid_exit_no_switch
|
|
SWITCH_USER_CR3
|
|
paranoid_exit_no_switch:
|
|
#endif
|
|
testl $1, %ebx /* swapgs needed? */
|
|
jnz paranoid_exit_no_swapgs
|
|
SWAPGS_UNSAFE_STACK
|
|
paranoid_exit_no_swapgs:
|
|
RESTORE_EXTRA_REGS
|
|
RESTORE_C_REGS
|
|
REMOVE_PT_GPREGS_FROM_STACK 8
|
|
INTERRUPT_RETURN
|
|
END(paranoid_exit)
|
|
|
|
/*
|
|
* Save all registers in pt_regs, and switch gs if needed.
|
|
*/
|
|
ENTRY(error_entry)
|
|
cld
|
|
SAVE_C_REGS 8
|
|
SAVE_EXTRA_REGS 8
|
|
/*
|
|
* error_entry() always returns with a kernel gsbase and
|
|
* CR3. We must also have a kernel CR3/gsbase before
|
|
* calling TRACE_IRQS_*. Just unconditionally switch to
|
|
* the kernel CR3 here.
|
|
*/
|
|
SWITCH_KERNEL_CR3
|
|
testb $3, CS+8(%rsp)
|
|
jz .Lerror_kernelspace
|
|
|
|
/*
|
|
* We entered from user mode or we're pretending to have entered
|
|
* from user mode due to an IRET fault.
|
|
*/
|
|
SWAPGS
|
|
FENCE_SWAPGS_USER_ENTRY
|
|
|
|
.Lerror_entry_from_usermode_after_swapgs:
|
|
/*
|
|
* We need to tell lockdep that IRQs are off. We can't do this until
|
|
* we fix gsbase, and we should do it before enter_from_user_mode
|
|
* (which can take locks).
|
|
*/
|
|
TRACE_IRQS_OFF
|
|
CALL_enter_from_user_mode
|
|
ret
|
|
|
|
.Lerror_entry_done_lfence:
|
|
FENCE_SWAPGS_KERNEL_ENTRY
|
|
.Lerror_entry_done:
|
|
TRACE_IRQS_OFF
|
|
ret
|
|
|
|
/*
|
|
* There are two places in the kernel that can potentially fault with
|
|
* usergs. Handle them here. B stepping K8s sometimes report a
|
|
* truncated RIP for IRET exceptions returning to compat mode. Check
|
|
* for these here too.
|
|
*/
|
|
.Lerror_kernelspace:
|
|
leaq native_irq_return_iret(%rip), %rcx
|
|
cmpq %rcx, RIP+8(%rsp)
|
|
je .Lerror_bad_iret
|
|
movl %ecx, %eax /* zero extend */
|
|
cmpq %rax, RIP+8(%rsp)
|
|
je .Lbstep_iret
|
|
cmpq $.Lgs_change, RIP+8(%rsp)
|
|
jne .Lerror_entry_done_lfence
|
|
|
|
/*
|
|
* hack: .Lgs_change can fail with user gsbase. If this happens, fix up
|
|
* gsbase and proceed. We'll fix up the exception and land in
|
|
* .Lgs_change's error handler with kernel gsbase.
|
|
*/
|
|
SWAPGS
|
|
FENCE_SWAPGS_USER_ENTRY
|
|
jmp .Lerror_entry_done
|
|
|
|
.Lbstep_iret:
|
|
/* Fix truncated RIP */
|
|
movq %rcx, RIP+8(%rsp)
|
|
/* fall through */
|
|
|
|
.Lerror_bad_iret:
|
|
/*
|
|
* We came from an IRET to user mode, so we have user gsbase.
|
|
* Switch to kernel gsbase:
|
|
*/
|
|
SWAPGS
|
|
FENCE_SWAPGS_USER_ENTRY
|
|
|
|
/*
|
|
* Pretend that the exception came from user mode: set up pt_regs
|
|
* as if we faulted immediately after IRET.
|
|
*/
|
|
mov %rsp, %rdi
|
|
call fixup_bad_iret
|
|
mov %rax, %rsp
|
|
jmp .Lerror_entry_from_usermode_after_swapgs
|
|
END(error_entry)
|
|
|
|
ENTRY(error_exit)
|
|
DISABLE_INTERRUPTS(CLBR_NONE)
|
|
TRACE_IRQS_OFF
|
|
testb $3, CS(%rsp)
|
|
jz retint_kernel
|
|
jmp retint_user
|
|
END(error_exit)
|
|
|
|
/* Runs on exception stack */
|
|
ENTRY(nmi)
|
|
/*
|
|
* Fix up the exception frame if we're on Xen.
|
|
* PARAVIRT_ADJUST_EXCEPTION_FRAME is guaranteed to push at most
|
|
* one value to the stack on native, so it may clobber the rdx
|
|
* scratch slot, but it won't clobber any of the important
|
|
* slots past it.
|
|
*
|
|
* Xen is a different story, because the Xen frame itself overlaps
|
|
* the "NMI executing" variable.
|
|
*/
|
|
PARAVIRT_ADJUST_EXCEPTION_FRAME
|
|
|
|
/*
|
|
* We allow breakpoints in NMIs. If a breakpoint occurs, then
|
|
* the iretq it performs will take us out of NMI context.
|
|
* This means that we can have nested NMIs where the next
|
|
* NMI is using the top of the stack of the previous NMI. We
|
|
* can't let it execute because the nested NMI will corrupt the
|
|
* stack of the previous NMI. NMI handlers are not re-entrant
|
|
* anyway.
|
|
*
|
|
* To handle this case we do the following:
|
|
* Check the a special location on the stack that contains
|
|
* a variable that is set when NMIs are executing.
|
|
* The interrupted task's stack is also checked to see if it
|
|
* is an NMI stack.
|
|
* If the variable is not set and the stack is not the NMI
|
|
* stack then:
|
|
* o Set the special variable on the stack
|
|
* o Copy the interrupt frame into an "outermost" location on the
|
|
* stack
|
|
* o Copy the interrupt frame into an "iret" location on the stack
|
|
* o Continue processing the NMI
|
|
* If the variable is set or the previous stack is the NMI stack:
|
|
* o Modify the "iret" location to jump to the repeat_nmi
|
|
* o return back to the first NMI
|
|
*
|
|
* Now on exit of the first NMI, we first clear the stack variable
|
|
* The NMI stack will tell any nested NMIs at that point that it is
|
|
* nested. Then we pop the stack normally with iret, and if there was
|
|
* a nested NMI that updated the copy interrupt stack frame, a
|
|
* jump will be made to the repeat_nmi code that will handle the second
|
|
* NMI.
|
|
*
|
|
* However, espfix prevents us from directly returning to userspace
|
|
* with a single IRET instruction. Similarly, IRET to user mode
|
|
* can fault. We therefore handle NMIs from user space like
|
|
* other IST entries.
|
|
*/
|
|
|
|
ASM_CLAC
|
|
|
|
/* Use %rdx as our temp variable throughout */
|
|
pushq %rdx
|
|
|
|
testb $3, CS-RIP+8(%rsp)
|
|
jz .Lnmi_from_kernel
|
|
|
|
/*
|
|
* NMI from user mode. We need to run on the thread stack, but we
|
|
* can't go through the normal entry paths: NMIs are masked, and
|
|
* we don't want to enable interrupts, because then we'll end
|
|
* up in an awkward situation in which IRQs are on but NMIs
|
|
* are off.
|
|
*
|
|
* We also must not push anything to the stack before switching
|
|
* stacks lest we corrupt the "NMI executing" variable.
|
|
*/
|
|
|
|
SWAPGS_UNSAFE_STACK
|
|
/*
|
|
* percpu variables are mapped with user CR3, so no need
|
|
* to switch CR3 here.
|
|
*/
|
|
cld
|
|
FENCE_SWAPGS_USER_ENTRY
|
|
movq %rsp, %rdx
|
|
movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
|
|
pushq 5*8(%rdx) /* pt_regs->ss */
|
|
pushq 4*8(%rdx) /* pt_regs->rsp */
|
|
pushq 3*8(%rdx) /* pt_regs->flags */
|
|
pushq 2*8(%rdx) /* pt_regs->cs */
|
|
pushq 1*8(%rdx) /* pt_regs->rip */
|
|
pushq $-1 /* pt_regs->orig_ax */
|
|
pushq %rdi /* pt_regs->di */
|
|
pushq %rsi /* pt_regs->si */
|
|
pushq (%rdx) /* pt_regs->dx */
|
|
pushq %rcx /* pt_regs->cx */
|
|
pushq %rax /* pt_regs->ax */
|
|
pushq %r8 /* pt_regs->r8 */
|
|
pushq %r9 /* pt_regs->r9 */
|
|
pushq %r10 /* pt_regs->r10 */
|
|
pushq %r11 /* pt_regs->r11 */
|
|
pushq %rbx /* pt_regs->rbx */
|
|
pushq %rbp /* pt_regs->rbp */
|
|
pushq %r12 /* pt_regs->r12 */
|
|
pushq %r13 /* pt_regs->r13 */
|
|
pushq %r14 /* pt_regs->r14 */
|
|
pushq %r15 /* pt_regs->r15 */
|
|
|
|
/*
|
|
* At this point we no longer need to worry about stack damage
|
|
* due to nesting -- we're on the normal thread stack and we're
|
|
* done with the NMI stack.
|
|
*/
|
|
|
|
movq %rsp, %rdi
|
|
movq $-1, %rsi
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
/* Unconditionally use kernel CR3 for do_nmi() */
|
|
/* %rax is saved above, so OK to clobber here */
|
|
ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
|
|
/* If PCID enabled, NOFLUSH now and NOFLUSH on return */
|
|
ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
|
|
pushq %rax
|
|
/* mask off "user" bit of pgd address and 12 PCID bits: */
|
|
andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
|
|
movq %rax, %cr3
|
|
2:
|
|
#endif
|
|
call do_nmi
|
|
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
/*
|
|
* Unconditionally restore CR3. I know we return to
|
|
* kernel code that needs user CR3, but do we ever return
|
|
* to "user mode" where we need the kernel CR3?
|
|
*/
|
|
ALTERNATIVE "", "popq %rax; movq %rax, %cr3", X86_FEATURE_KAISER
|
|
#endif
|
|
|
|
/*
|
|
* Return back to user mode. We must *not* do the normal exit
|
|
* work, because we don't want to enable interrupts. Do not
|
|
* switch to user CR3: we might be going back to kernel code
|
|
* that had a user CR3 set.
|
|
*/
|
|
SWAPGS
|
|
jmp restore_c_regs_and_iret
|
|
|
|
.Lnmi_from_kernel:
|
|
/*
|
|
* Here's what our stack frame will look like:
|
|
* +---------------------------------------------------------+
|
|
* | original SS |
|
|
* | original Return RSP |
|
|
* | original RFLAGS |
|
|
* | original CS |
|
|
* | original RIP |
|
|
* +---------------------------------------------------------+
|
|
* | temp storage for rdx |
|
|
* +---------------------------------------------------------+
|
|
* | "NMI executing" variable |
|
|
* +---------------------------------------------------------+
|
|
* | iret SS } Copied from "outermost" frame |
|
|
* | iret Return RSP } on each loop iteration; overwritten |
|
|
* | iret RFLAGS } by a nested NMI to force another |
|
|
* | iret CS } iteration if needed. |
|
|
* | iret RIP } |
|
|
* +---------------------------------------------------------+
|
|
* | outermost SS } initialized in first_nmi; |
|
|
* | outermost Return RSP } will not be changed before |
|
|
* | outermost RFLAGS } NMI processing is done. |
|
|
* | outermost CS } Copied to "iret" frame on each |
|
|
* | outermost RIP } iteration. |
|
|
* +---------------------------------------------------------+
|
|
* | pt_regs |
|
|
* +---------------------------------------------------------+
|
|
*
|
|
* The "original" frame is used by hardware. Before re-enabling
|
|
* NMIs, we need to be done with it, and we need to leave enough
|
|
* space for the asm code here.
|
|
*
|
|
* We return by executing IRET while RSP points to the "iret" frame.
|
|
* That will either return for real or it will loop back into NMI
|
|
* processing.
|
|
*
|
|
* The "outermost" frame is copied to the "iret" frame on each
|
|
* iteration of the loop, so each iteration starts with the "iret"
|
|
* frame pointing to the final return target.
|
|
*/
|
|
|
|
/*
|
|
* Determine whether we're a nested NMI.
|
|
*
|
|
* If we interrupted kernel code between repeat_nmi and
|
|
* end_repeat_nmi, then we are a nested NMI. We must not
|
|
* modify the "iret" frame because it's being written by
|
|
* the outer NMI. That's okay; the outer NMI handler is
|
|
* about to about to call do_nmi anyway, so we can just
|
|
* resume the outer NMI.
|
|
*/
|
|
|
|
movq $repeat_nmi, %rdx
|
|
cmpq 8(%rsp), %rdx
|
|
ja 1f
|
|
movq $end_repeat_nmi, %rdx
|
|
cmpq 8(%rsp), %rdx
|
|
ja nested_nmi_out
|
|
1:
|
|
|
|
/*
|
|
* Now check "NMI executing". If it's set, then we're nested.
|
|
* This will not detect if we interrupted an outer NMI just
|
|
* before IRET.
|
|
*/
|
|
cmpl $1, -8(%rsp)
|
|
je nested_nmi
|
|
|
|
/*
|
|
* Now test if the previous stack was an NMI stack. This covers
|
|
* the case where we interrupt an outer NMI after it clears
|
|
* "NMI executing" but before IRET. We need to be careful, though:
|
|
* there is one case in which RSP could point to the NMI stack
|
|
* despite there being no NMI active: naughty userspace controls
|
|
* RSP at the very beginning of the SYSCALL targets. We can
|
|
* pull a fast one on naughty userspace, though: we program
|
|
* SYSCALL to mask DF, so userspace cannot cause DF to be set
|
|
* if it controls the kernel's RSP. We set DF before we clear
|
|
* "NMI executing".
|
|
*/
|
|
lea 6*8(%rsp), %rdx
|
|
/* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
|
|
cmpq %rdx, 4*8(%rsp)
|
|
/* If the stack pointer is above the NMI stack, this is a normal NMI */
|
|
ja first_nmi
|
|
|
|
subq $EXCEPTION_STKSZ, %rdx
|
|
cmpq %rdx, 4*8(%rsp)
|
|
/* If it is below the NMI stack, it is a normal NMI */
|
|
jb first_nmi
|
|
|
|
/* Ah, it is within the NMI stack. */
|
|
|
|
testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
|
|
jz first_nmi /* RSP was user controlled. */
|
|
|
|
/* This is a nested NMI. */
|
|
|
|
nested_nmi:
|
|
/*
|
|
* Modify the "iret" frame to point to repeat_nmi, forcing another
|
|
* iteration of NMI handling.
|
|
*/
|
|
subq $8, %rsp
|
|
leaq -10*8(%rsp), %rdx
|
|
pushq $__KERNEL_DS
|
|
pushq %rdx
|
|
pushfq
|
|
pushq $__KERNEL_CS
|
|
pushq $repeat_nmi
|
|
|
|
/* Put stack back */
|
|
addq $(6*8), %rsp
|
|
|
|
nested_nmi_out:
|
|
popq %rdx
|
|
|
|
/* We are returning to kernel mode, so this cannot result in a fault. */
|
|
INTERRUPT_RETURN
|
|
|
|
first_nmi:
|
|
/* Restore rdx. */
|
|
movq (%rsp), %rdx
|
|
|
|
/* Make room for "NMI executing". */
|
|
pushq $0
|
|
|
|
/* Leave room for the "iret" frame */
|
|
subq $(5*8), %rsp
|
|
|
|
/* Copy the "original" frame to the "outermost" frame */
|
|
.rept 5
|
|
pushq 11*8(%rsp)
|
|
.endr
|
|
|
|
/* Everything up to here is safe from nested NMIs */
|
|
|
|
#ifdef CONFIG_DEBUG_ENTRY
|
|
/*
|
|
* For ease of testing, unmask NMIs right away. Disabled by
|
|
* default because IRET is very expensive.
|
|
*/
|
|
pushq $0 /* SS */
|
|
pushq %rsp /* RSP (minus 8 because of the previous push) */
|
|
addq $8, (%rsp) /* Fix up RSP */
|
|
pushfq /* RFLAGS */
|
|
pushq $__KERNEL_CS /* CS */
|
|
pushq $1f /* RIP */
|
|
INTERRUPT_RETURN /* continues at repeat_nmi below */
|
|
1:
|
|
#endif
|
|
|
|
repeat_nmi:
|
|
/*
|
|
* If there was a nested NMI, the first NMI's iret will return
|
|
* here. But NMIs are still enabled and we can take another
|
|
* nested NMI. The nested NMI checks the interrupted RIP to see
|
|
* if it is between repeat_nmi and end_repeat_nmi, and if so
|
|
* it will just return, as we are about to repeat an NMI anyway.
|
|
* This makes it safe to copy to the stack frame that a nested
|
|
* NMI will update.
|
|
*
|
|
* RSP is pointing to "outermost RIP". gsbase is unknown, but, if
|
|
* we're repeating an NMI, gsbase has the same value that it had on
|
|
* the first iteration. paranoid_entry will load the kernel
|
|
* gsbase if needed before we call do_nmi. "NMI executing"
|
|
* is zero.
|
|
*/
|
|
movq $1, 10*8(%rsp) /* Set "NMI executing". */
|
|
|
|
/*
|
|
* Copy the "outermost" frame to the "iret" frame. NMIs that nest
|
|
* here must not modify the "iret" frame while we're writing to
|
|
* it or it will end up containing garbage.
|
|
*/
|
|
addq $(10*8), %rsp
|
|
.rept 5
|
|
pushq -6*8(%rsp)
|
|
.endr
|
|
subq $(5*8), %rsp
|
|
end_repeat_nmi:
|
|
|
|
/*
|
|
* Everything below this point can be preempted by a nested NMI.
|
|
* If this happens, then the inner NMI will change the "iret"
|
|
* frame to point back to repeat_nmi.
|
|
*/
|
|
pushq $-1 /* ORIG_RAX: no syscall to restart */
|
|
ALLOC_PT_GPREGS_ON_STACK
|
|
|
|
/*
|
|
* Use the same approach as paranoid_entry to handle SWAPGS, but
|
|
* without CR3 handling since we do that differently in NMIs. No
|
|
* need to use paranoid_exit as we should not be calling schedule
|
|
* in NMI context. Even with normal interrupts enabled. An NMI
|
|
* should not be setting NEED_RESCHED or anything that normal
|
|
* interrupts and exceptions might do.
|
|
*/
|
|
cld
|
|
SAVE_C_REGS
|
|
SAVE_EXTRA_REGS
|
|
movl $1, %ebx
|
|
movl $MSR_GS_BASE, %ecx
|
|
rdmsr
|
|
testl %edx, %edx
|
|
js 1f /* negative -> in kernel */
|
|
SWAPGS
|
|
xorl %ebx, %ebx
|
|
1:
|
|
movq %rsp, %rdi
|
|
movq $-1, %rsi
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
/* Unconditionally use kernel CR3 for do_nmi() */
|
|
/* %rax is saved above, so OK to clobber here */
|
|
ALTERNATIVE "jmp 2f", "movq %cr3, %rax", X86_FEATURE_KAISER
|
|
/* If PCID enabled, NOFLUSH now and NOFLUSH on return */
|
|
ALTERNATIVE "", "bts $63, %rax", X86_FEATURE_PCID
|
|
pushq %rax
|
|
/* mask off "user" bit of pgd address and 12 PCID bits: */
|
|
andq $(~(X86_CR3_PCID_ASID_MASK | KAISER_SHADOW_PGD_OFFSET)), %rax
|
|
movq %rax, %cr3
|
|
2:
|
|
#endif
|
|
FENCE_SWAPGS_KERNEL_ENTRY
|
|
|
|
/* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
|
|
call do_nmi
|
|
|
|
#ifdef CONFIG_PAGE_TABLE_ISOLATION
|
|
/*
|
|
* Unconditionally restore CR3. We might be returning to
|
|
* kernel code that needs user CR3, like just just before
|
|
* a sysret.
|
|
*/
|
|
ALTERNATIVE "", "popq %rax; movq %rax, %cr3", X86_FEATURE_KAISER
|
|
#endif
|
|
|
|
testl %ebx, %ebx /* swapgs needed? */
|
|
jnz nmi_restore
|
|
nmi_swapgs:
|
|
/* We fixed up CR3 above, so no need to switch it here */
|
|
SWAPGS_UNSAFE_STACK
|
|
nmi_restore:
|
|
RESTORE_EXTRA_REGS
|
|
RESTORE_C_REGS
|
|
|
|
/* Point RSP at the "iret" frame. */
|
|
REMOVE_PT_GPREGS_FROM_STACK 6*8
|
|
|
|
/*
|
|
* Clear "NMI executing". Set DF first so that we can easily
|
|
* distinguish the remaining code between here and IRET from
|
|
* the SYSCALL entry and exit paths. On a native kernel, we
|
|
* could just inspect RIP, but, on paravirt kernels,
|
|
* INTERRUPT_RETURN can translate into a jump into a
|
|
* hypercall page.
|
|
*/
|
|
std
|
|
movq $0, 5*8(%rsp) /* clear "NMI executing" */
|
|
|
|
/*
|
|
* INTERRUPT_RETURN reads the "iret" frame and exits the NMI
|
|
* stack in a single instruction. We are returning to kernel
|
|
* mode, so this cannot result in a fault.
|
|
*/
|
|
INTERRUPT_RETURN
|
|
END(nmi)
|
|
|
|
ENTRY(ignore_sysret)
|
|
mov $-ENOSYS, %eax
|
|
sysret
|
|
END(ignore_sysret)
|
|
|
|
ENTRY(rewind_stack_do_exit)
|
|
/* Prevent any naive code from trying to unwind to our caller. */
|
|
xorl %ebp, %ebp
|
|
|
|
movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
|
|
leaq -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%rax), %rsp
|
|
|
|
call do_exit
|
|
1: jmp 1b
|
|
END(rewind_stack_do_exit)
|