666 lines
17 KiB
C
666 lines
17 KiB
C
/*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* General FPU state handling cleanups
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* Gareth Hughes <gareth@valinux.com>, May 2000
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* x86-64 work by Andi Kleen 2002
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*/
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#ifndef _ASM_X86_FPU_INTERNAL_H
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#define _ASM_X86_FPU_INTERNAL_H
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#include <linux/compat.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <asm/user.h>
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#include <asm/fpu/api.h>
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#include <asm/fpu/xstate.h>
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#include <asm/cpufeature.h>
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#include <asm/trace/fpu.h>
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/*
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* High level FPU state handling functions:
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*/
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extern void fpu__activate_curr(struct fpu *fpu);
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extern void fpu__activate_fpstate_read(struct fpu *fpu);
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extern void fpu__activate_fpstate_write(struct fpu *fpu);
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extern void fpu__current_fpstate_write_begin(void);
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extern void fpu__current_fpstate_write_end(void);
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extern void fpu__save(struct fpu *fpu);
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extern void fpu__restore(struct fpu *fpu);
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extern int fpu__restore_sig(void __user *buf, int ia32_frame);
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extern void fpu__drop(struct fpu *fpu);
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extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu);
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extern void fpu__clear(struct fpu *fpu);
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extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
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extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate);
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/*
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* Boot time FPU initialization functions:
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*/
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extern void fpu__init_cpu(void);
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extern void fpu__init_system_xstate(void);
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extern void fpu__init_cpu_xstate(void);
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extern void fpu__init_system(struct cpuinfo_x86 *c);
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extern void fpu__init_check_bugs(void);
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extern void fpu__resume_cpu(void);
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extern u64 fpu__get_supported_xfeatures_mask(void);
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/*
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* Debugging facility:
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*/
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#ifdef CONFIG_X86_DEBUG_FPU
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# define WARN_ON_FPU(x) WARN_ON_ONCE(x)
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#else
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# define WARN_ON_FPU(x) ({ (void)(x); 0; })
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#endif
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/*
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* FPU related CPU feature flag helper routines:
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*/
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static __always_inline __pure bool use_xsaveopt(void)
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{
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return static_cpu_has(X86_FEATURE_XSAVEOPT);
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}
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static __always_inline __pure bool use_xsave(void)
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{
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return static_cpu_has(X86_FEATURE_XSAVE);
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}
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static __always_inline __pure bool use_fxsr(void)
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{
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return static_cpu_has(X86_FEATURE_FXSR);
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}
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/*
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* fpstate handling functions:
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*/
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extern union fpregs_state init_fpstate;
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extern void fpstate_init(union fpregs_state *state);
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#ifdef CONFIG_MATH_EMULATION
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extern void fpstate_init_soft(struct swregs_state *soft);
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#else
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static inline void fpstate_init_soft(struct swregs_state *soft) {}
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#endif
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static inline void fpstate_init_fxstate(struct fxregs_state *fx)
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{
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fx->cwd = 0x37f;
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fx->mxcsr = MXCSR_DEFAULT;
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}
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extern void fpstate_sanitize_xstate(struct fpu *fpu);
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#define user_insn(insn, output, input...) \
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({ \
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int err; \
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\
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might_fault(); \
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\
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asm volatile(ASM_STAC "\n" \
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"1:" #insn "\n\t" \
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"2: " ASM_CLAC "\n" \
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".section .fixup,\"ax\"\n" \
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"3: movl $-1,%[err]\n" \
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" jmp 2b\n" \
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".previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: [err] "=r" (err), output \
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: "0"(0), input); \
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err; \
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})
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#define check_insn(insn, output, input...) \
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({ \
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int err; \
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asm volatile("1:" #insn "\n\t" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: movl $-1,%[err]\n" \
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" jmp 2b\n" \
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".previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: [err] "=r" (err), output \
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: "0"(0), input); \
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err; \
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})
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static inline int copy_fregs_to_user(struct fregs_state __user *fx)
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{
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return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
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}
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static inline int copy_fxregs_to_user(struct fxregs_state __user *fx)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
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else if (IS_ENABLED(CONFIG_AS_FXSAVEQ))
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return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
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/* See comment in copy_fxregs_to_kernel() below. */
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return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
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}
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static inline void copy_kernel_to_fxregs(struct fxregs_state *fx)
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{
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int err;
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if (IS_ENABLED(CONFIG_X86_32)) {
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err = check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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} else {
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if (IS_ENABLED(CONFIG_AS_FXSAVEQ)) {
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err = check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
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} else {
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/* See comment in copy_fxregs_to_kernel() below. */
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err = check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), "m" (*fx));
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}
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}
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/* Copying from a kernel buffer to FPU registers should never fail: */
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WARN_ON_FPU(err);
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}
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static inline int copy_user_to_fxregs(struct fxregs_state __user *fx)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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else if (IS_ENABLED(CONFIG_AS_FXSAVEQ))
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return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
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/* See comment in copy_fxregs_to_kernel() below. */
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return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
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"m" (*fx));
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}
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static inline void copy_kernel_to_fregs(struct fregs_state *fx)
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{
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int err = check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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WARN_ON_FPU(err);
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}
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static inline int copy_user_to_fregs(struct fregs_state __user *fx)
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{
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return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline void copy_fxregs_to_kernel(struct fpu *fpu)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave));
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else if (IS_ENABLED(CONFIG_AS_FXSAVEQ))
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asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave));
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else {
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/* Using "rex64; fxsave %0" is broken because, if the memory
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* operand uses any extended registers for addressing, a second
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* REX prefix will be generated (to the assembler, rex64
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* followed by semicolon is a separate instruction), and hence
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* the 64-bitness is lost.
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*
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* Using "fxsaveq %0" would be the ideal choice, but is only
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* supported starting with gas 2.16.
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*
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* Using, as a workaround, the properly prefixed form below
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* isn't accepted by any binutils version so far released,
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* complaining that the same type of prefix is used twice if
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* an extended register is needed for addressing (fix submitted
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* to mainline 2005-11-21).
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*
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* asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave));
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*
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* This, however, we can work around by forcing the compiler to
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* select an addressing mode that doesn't require extended
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* registers.
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*/
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asm volatile( "rex64/fxsave (%[fx])"
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: "=m" (fpu->state.fxsave)
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: [fx] "R" (&fpu->state.fxsave));
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}
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}
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/* These macros all use (%edi)/(%rdi) as the single memory argument. */
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#define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27"
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#define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37"
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#define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
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#define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
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#define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
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#define XSTATE_OP(op, st, lmask, hmask, err) \
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asm volatile("1:" op "\n\t" \
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"xor %[err], %[err]\n" \
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"2:\n\t" \
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".pushsection .fixup,\"ax\"\n\t" \
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"3: movl $-2,%[err]\n\t" \
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"jmp 2b\n\t" \
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".popsection\n\t" \
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_ASM_EXTABLE(1b, 3b) \
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: [err] "=r" (err) \
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: "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
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: "memory")
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/*
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* If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact
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* format and supervisor states in addition to modified optimization in
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* XSAVEOPT.
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*
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* Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT
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* supports modified optimization which is not supported by XSAVE.
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*
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* We use XSAVE as a fallback.
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*
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* The 661 label is defined in the ALTERNATIVE* macros as the address of the
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* original instruction which gets replaced. We need to use it here as the
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* address of the instruction where we might get an exception at.
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*/
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#define XSTATE_XSAVE(st, lmask, hmask, err) \
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asm volatile(ALTERNATIVE_2(XSAVE, \
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XSAVEOPT, X86_FEATURE_XSAVEOPT, \
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XSAVES, X86_FEATURE_XSAVES) \
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"\n" \
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"xor %[err], %[err]\n" \
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"3:\n" \
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".pushsection .fixup,\"ax\"\n" \
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"4: movl $-2, %[err]\n" \
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"jmp 3b\n" \
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".popsection\n" \
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_ASM_EXTABLE(661b, 4b) \
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: [err] "=r" (err) \
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: "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
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: "memory")
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/*
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* Use XRSTORS to restore context if it is enabled. XRSTORS supports compact
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* XSAVE area format.
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*/
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#define XSTATE_XRESTORE(st, lmask, hmask, err) \
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asm volatile(ALTERNATIVE(XRSTOR, \
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XRSTORS, X86_FEATURE_XSAVES) \
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"\n" \
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"xor %[err], %[err]\n" \
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"3:\n" \
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".pushsection .fixup,\"ax\"\n" \
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"4: movl $-2, %[err]\n" \
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"jmp 3b\n" \
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".popsection\n" \
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_ASM_EXTABLE(661b, 4b) \
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: [err] "=r" (err) \
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: "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
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: "memory")
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/*
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* This function is called only during boot time when x86 caps are not set
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* up and alternative can not be used yet.
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*/
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static inline void copy_xregs_to_kernel_booting(struct xregs_state *xstate)
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{
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u64 mask = -1;
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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WARN_ON(system_state != SYSTEM_BOOTING);
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if (static_cpu_has(X86_FEATURE_XSAVES))
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XSTATE_OP(XSAVES, xstate, lmask, hmask, err);
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else
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XSTATE_OP(XSAVE, xstate, lmask, hmask, err);
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/* We should never fault when copying to a kernel buffer: */
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WARN_ON_FPU(err);
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}
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/*
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* This function is called only during boot time when x86 caps are not set
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* up and alternative can not be used yet.
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*/
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static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate)
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{
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u64 mask = -1;
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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WARN_ON(system_state != SYSTEM_BOOTING);
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if (static_cpu_has(X86_FEATURE_XSAVES))
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XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
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else
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XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
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/* We should never fault when copying from a kernel buffer: */
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WARN_ON_FPU(err);
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}
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/*
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* Save processor xstate to xsave area.
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*/
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static inline void copy_xregs_to_kernel(struct xregs_state *xstate)
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{
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u64 mask = -1;
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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WARN_ON(!alternatives_patched);
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XSTATE_XSAVE(xstate, lmask, hmask, err);
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/* We should never fault when copying to a kernel buffer: */
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WARN_ON_FPU(err);
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}
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/*
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* Restore processor xstate from xsave area.
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*/
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static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask)
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{
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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XSTATE_XRESTORE(xstate, lmask, hmask, err);
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/* We should never fault when copying from a kernel buffer: */
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WARN_ON_FPU(err);
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}
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/*
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* Save xstate to user space xsave area.
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*
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* We don't use modified optimization because xrstor/xrstors might track
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* a different application.
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*
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* We don't use compacted format xsave area for
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* backward compatibility for old applications which don't understand
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* compacted format of xsave area.
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*/
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static inline int copy_xregs_to_user(struct xregs_state __user *buf)
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{
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int err;
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/*
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* Clear the xsave header first, so that reserved fields are
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* initialized to zero.
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*/
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err = __clear_user(&buf->header, sizeof(buf->header));
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if (unlikely(err))
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return -EFAULT;
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stac();
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XSTATE_OP(XSAVE, buf, -1, -1, err);
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clac();
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return err;
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}
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/*
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* Restore xstate from user space xsave area.
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*/
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static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask)
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{
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struct xregs_state *xstate = ((__force struct xregs_state *)buf);
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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stac();
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XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
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clac();
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return err;
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}
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/*
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* These must be called with preempt disabled. Returns
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* 'true' if the FPU state is still intact and we can
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* keep registers active.
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*
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* The legacy FNSAVE instruction cleared all FPU state
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* unconditionally, so registers are essentially destroyed.
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* Modern FPU state can be kept in registers, if there are
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* no pending FP exceptions.
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*/
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static inline int copy_fpregs_to_fpstate(struct fpu *fpu)
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{
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if (likely(use_xsave())) {
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copy_xregs_to_kernel(&fpu->state.xsave);
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return 1;
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}
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if (likely(use_fxsr())) {
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copy_fxregs_to_kernel(fpu);
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return 1;
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}
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/*
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* Legacy FPU register saving, FNSAVE always clears FPU registers,
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* so we have to mark them inactive:
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*/
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asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave));
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return 0;
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}
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static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate)
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{
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if (use_xsave()) {
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copy_kernel_to_xregs(&fpstate->xsave, -1);
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} else {
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if (use_fxsr())
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copy_kernel_to_fxregs(&fpstate->fxsave);
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else
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copy_kernel_to_fregs(&fpstate->fsave);
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}
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}
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static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate)
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{
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/*
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* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
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* pending. Clear the x87 state here by setting it to fixed values.
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* "m" is a random variable that should be in L1.
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*/
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if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
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asm volatile(
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"fnclex\n\t"
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"emms\n\t"
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"fildl %P[addr]" /* set F?P to defined value */
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: : [addr] "m" (fpstate));
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}
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__copy_kernel_to_fpregs(fpstate);
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}
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extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size);
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/*
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* FPU context switch related helper methods:
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*/
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DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
|
|
|
|
/*
|
|
* Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx,
|
|
* on this CPU.
|
|
*
|
|
* This will disable any lazy FPU state restore of the current FPU state,
|
|
* but if the current thread owns the FPU, it will still be saved by.
|
|
*/
|
|
static inline void __cpu_disable_lazy_restore(unsigned int cpu)
|
|
{
|
|
per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
|
|
}
|
|
|
|
static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu)
|
|
{
|
|
return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
|
|
}
|
|
|
|
|
|
static inline void __fpregs_deactivate(struct fpu *fpu)
|
|
{
|
|
WARN_ON_FPU(!fpu->fpregs_active);
|
|
|
|
fpu->fpregs_active = 0;
|
|
this_cpu_write(fpu_fpregs_owner_ctx, NULL);
|
|
trace_x86_fpu_regs_deactivated(fpu);
|
|
}
|
|
|
|
static inline void __fpregs_activate(struct fpu *fpu)
|
|
{
|
|
WARN_ON_FPU(fpu->fpregs_active);
|
|
|
|
fpu->fpregs_active = 1;
|
|
this_cpu_write(fpu_fpregs_owner_ctx, fpu);
|
|
trace_x86_fpu_regs_activated(fpu);
|
|
}
|
|
|
|
/*
|
|
* The question "does this thread have fpu access?"
|
|
* is slightly racy, since preemption could come in
|
|
* and revoke it immediately after the test.
|
|
*
|
|
* However, even in that very unlikely scenario,
|
|
* we can just assume we have FPU access - typically
|
|
* to save the FP state - we'll just take a #NM
|
|
* fault and get the FPU access back.
|
|
*/
|
|
static inline int fpregs_active(void)
|
|
{
|
|
return current->thread.fpu.fpregs_active;
|
|
}
|
|
|
|
/*
|
|
* These generally need preemption protection to work,
|
|
* do try to avoid using these on their own.
|
|
*/
|
|
static inline void fpregs_activate(struct fpu *fpu)
|
|
{
|
|
__fpregs_activate(fpu);
|
|
}
|
|
|
|
static inline void fpregs_deactivate(struct fpu *fpu)
|
|
{
|
|
__fpregs_deactivate(fpu);
|
|
}
|
|
|
|
/*
|
|
* FPU state switching for scheduling.
|
|
*
|
|
* This is a two-stage process:
|
|
*
|
|
* - switch_fpu_prepare() saves the old state and
|
|
* sets the new state of the CR0.TS bit. This is
|
|
* done within the context of the old process.
|
|
*
|
|
* - switch_fpu_finish() restores the new state as
|
|
* necessary.
|
|
*/
|
|
typedef struct { int preload; } fpu_switch_t;
|
|
|
|
static inline fpu_switch_t
|
|
switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu)
|
|
{
|
|
fpu_switch_t fpu;
|
|
|
|
/*
|
|
* If the task has used the math, pre-load the FPU on xsave processors
|
|
* or if the past 5 consecutive context-switches used math.
|
|
*/
|
|
fpu.preload = static_cpu_has(X86_FEATURE_FPU) &&
|
|
new_fpu->fpstate_active;
|
|
|
|
if (old_fpu->fpregs_active) {
|
|
if (!copy_fpregs_to_fpstate(old_fpu))
|
|
old_fpu->last_cpu = -1;
|
|
else
|
|
old_fpu->last_cpu = cpu;
|
|
|
|
/* But leave fpu_fpregs_owner_ctx! */
|
|
old_fpu->fpregs_active = 0;
|
|
trace_x86_fpu_regs_deactivated(old_fpu);
|
|
|
|
/* Don't change CR0.TS if we just switch! */
|
|
if (fpu.preload) {
|
|
__fpregs_activate(new_fpu);
|
|
trace_x86_fpu_regs_activated(new_fpu);
|
|
prefetch(&new_fpu->state);
|
|
}
|
|
} else {
|
|
old_fpu->last_cpu = -1;
|
|
if (fpu.preload) {
|
|
if (fpu_want_lazy_restore(new_fpu, cpu))
|
|
fpu.preload = 0;
|
|
else
|
|
prefetch(&new_fpu->state);
|
|
fpregs_activate(new_fpu);
|
|
}
|
|
}
|
|
return fpu;
|
|
}
|
|
|
|
/*
|
|
* Misc helper functions:
|
|
*/
|
|
|
|
/*
|
|
* By the time this gets called, we've already cleared CR0.TS and
|
|
* given the process the FPU if we are going to preload the FPU
|
|
* state - all we need to do is to conditionally restore the register
|
|
* state itself.
|
|
*/
|
|
static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch)
|
|
{
|
|
if (fpu_switch.preload)
|
|
copy_kernel_to_fpregs(&new_fpu->state);
|
|
}
|
|
|
|
/*
|
|
* Needs to be preemption-safe.
|
|
*
|
|
* NOTE! user_fpu_begin() must be used only immediately before restoring
|
|
* the save state. It does not do any saving/restoring on its own. In
|
|
* lazy FPU mode, it is just an optimization to avoid a #NM exception,
|
|
* the task can lose the FPU right after preempt_enable().
|
|
*/
|
|
static inline void user_fpu_begin(void)
|
|
{
|
|
struct fpu *fpu = ¤t->thread.fpu;
|
|
|
|
preempt_disable();
|
|
if (!fpregs_active())
|
|
fpregs_activate(fpu);
|
|
preempt_enable();
|
|
}
|
|
|
|
/*
|
|
* MXCSR and XCR definitions:
|
|
*/
|
|
|
|
extern unsigned int mxcsr_feature_mask;
|
|
|
|
#define XCR_XFEATURE_ENABLED_MASK 0x00000000
|
|
|
|
static inline u64 xgetbv(u32 index)
|
|
{
|
|
u32 eax, edx;
|
|
|
|
asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
|
|
: "=a" (eax), "=d" (edx)
|
|
: "c" (index));
|
|
return eax + ((u64)edx << 32);
|
|
}
|
|
|
|
static inline void xsetbv(u32 index, u64 value)
|
|
{
|
|
u32 eax = value;
|
|
u32 edx = value >> 32;
|
|
|
|
asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
|
|
: : "a" (eax), "d" (edx), "c" (index));
|
|
}
|
|
|
|
#endif /* _ASM_X86_FPU_INTERNAL_H */
|