326 lines
8.5 KiB
C
326 lines
8.5 KiB
C
#ifndef _ASM_X86_TLBFLUSH_H
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#define _ASM_X86_TLBFLUSH_H
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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#include <asm/special_insns.h>
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#include <asm/smp.h>
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static inline void __invpcid(unsigned long pcid, unsigned long addr,
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unsigned long type)
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{
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struct { u64 d[2]; } desc = { { pcid, addr } };
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/*
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* The memory clobber is because the whole point is to invalidate
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* stale TLB entries and, especially if we're flushing global
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* mappings, we don't want the compiler to reorder any subsequent
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* memory accesses before the TLB flush.
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*
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* The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
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* invpcid (%rcx), %rax in long mode.
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*/
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asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
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: : "m" (desc), "a" (type), "c" (&desc) : "memory");
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}
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#define INVPCID_TYPE_INDIV_ADDR 0
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#define INVPCID_TYPE_SINGLE_CTXT 1
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#define INVPCID_TYPE_ALL_INCL_GLOBAL 2
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#define INVPCID_TYPE_ALL_NON_GLOBAL 3
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/* Flush all mappings for a given pcid and addr, not including globals. */
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static inline void invpcid_flush_one(unsigned long pcid,
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unsigned long addr)
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{
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__invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
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}
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/* Flush all mappings for a given PCID, not including globals. */
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static inline void invpcid_flush_single_context(unsigned long pcid)
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{
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__invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
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}
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/* Flush all mappings, including globals, for all PCIDs. */
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static inline void invpcid_flush_all(void)
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{
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__invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
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}
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/* Flush all mappings for all PCIDs except globals. */
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static inline void invpcid_flush_all_nonglobals(void)
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{
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__invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define __flush_tlb() __native_flush_tlb()
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#define __flush_tlb_global() __native_flush_tlb_global()
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#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
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#endif
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struct tlb_state {
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struct mm_struct *active_mm;
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int state;
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/* Last user mm for optimizing IBPB */
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union {
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struct mm_struct *last_user_mm;
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unsigned long last_user_mm_ibpb;
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};
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/*
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* Access to this CR4 shadow and to H/W CR4 is protected by
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* disabling interrupts when modifying either one.
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*/
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unsigned long cr4;
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};
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DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
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/* Initialize cr4 shadow for this CPU. */
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static inline void cr4_init_shadow(void)
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{
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this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
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}
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/* Set in this cpu's CR4. */
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static inline void cr4_set_bits(unsigned long mask)
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{
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unsigned long cr4;
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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if ((cr4 | mask) != cr4) {
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cr4 |= mask;
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this_cpu_write(cpu_tlbstate.cr4, cr4);
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__write_cr4(cr4);
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}
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}
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/* Clear in this cpu's CR4. */
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static inline void cr4_clear_bits(unsigned long mask)
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{
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unsigned long cr4;
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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if ((cr4 & ~mask) != cr4) {
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cr4 &= ~mask;
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this_cpu_write(cpu_tlbstate.cr4, cr4);
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__write_cr4(cr4);
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}
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}
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static inline void cr4_toggle_bits(unsigned long mask)
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{
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unsigned long cr4;
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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cr4 ^= mask;
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this_cpu_write(cpu_tlbstate.cr4, cr4);
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__write_cr4(cr4);
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}
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/* Read the CR4 shadow. */
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static inline unsigned long cr4_read_shadow(void)
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{
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return this_cpu_read(cpu_tlbstate.cr4);
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}
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/*
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* Save some of cr4 feature set we're using (e.g. Pentium 4MB
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* enable and PPro Global page enable), so that any CPU's that boot
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* up after us can get the correct flags. This should only be used
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* during boot on the boot cpu.
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*/
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extern unsigned long mmu_cr4_features;
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extern u32 *trampoline_cr4_features;
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static inline void cr4_set_bits_and_update_boot(unsigned long mask)
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{
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mmu_cr4_features |= mask;
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if (trampoline_cr4_features)
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*trampoline_cr4_features = mmu_cr4_features;
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cr4_set_bits(mask);
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}
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/*
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* Declare a couple of kaiser interfaces here for convenience,
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* to avoid the need for asm/kaiser.h in unexpected places.
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*/
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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extern int kaiser_enabled;
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extern void kaiser_setup_pcid(void);
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extern void kaiser_flush_tlb_on_return_to_user(void);
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#else
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#define kaiser_enabled 0
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static inline void kaiser_setup_pcid(void)
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{
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}
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static inline void kaiser_flush_tlb_on_return_to_user(void)
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{
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}
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#endif
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static inline void __native_flush_tlb(void)
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{
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/*
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* If current->mm == NULL then we borrow a mm which may change during a
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* task switch and therefore we must not be preempted while we write CR3
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* back:
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*/
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preempt_disable();
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if (kaiser_enabled)
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kaiser_flush_tlb_on_return_to_user();
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native_write_cr3(native_read_cr3());
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preempt_enable();
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}
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static inline void __native_flush_tlb_global_irq_disabled(void)
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{
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unsigned long cr4;
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cr4 = this_cpu_read(cpu_tlbstate.cr4);
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if (cr4 & X86_CR4_PGE) {
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/* clear PGE and flush TLB of all entries */
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native_write_cr4(cr4 & ~X86_CR4_PGE);
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/* restore PGE as it was before */
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native_write_cr4(cr4);
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} else {
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/* do it with cr3, letting kaiser flush user PCID */
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__native_flush_tlb();
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}
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}
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static inline void __native_flush_tlb_global(void)
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{
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unsigned long flags;
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if (this_cpu_has(X86_FEATURE_INVPCID)) {
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/*
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* Using INVPCID is considerably faster than a pair of writes
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* to CR4 sandwiched inside an IRQ flag save/restore.
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*
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* Note, this works with CR4.PCIDE=0 or 1.
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*/
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invpcid_flush_all();
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return;
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}
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/*
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* Read-modify-write to CR4 - protect it from preemption and
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* from interrupts. (Use the raw variant because this code can
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* be called from deep inside debugging code.)
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*/
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raw_local_irq_save(flags);
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__native_flush_tlb_global_irq_disabled();
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raw_local_irq_restore(flags);
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}
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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/*
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* SIMICS #GP's if you run INVPCID with type 2/3
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* and X86_CR4_PCIDE clear. Shame!
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*
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* The ASIDs used below are hard-coded. But, we must not
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* call invpcid(type=1/2) before CR4.PCIDE=1. Just call
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* invlpg in the case we are called early.
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*/
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if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE)) {
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if (kaiser_enabled)
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kaiser_flush_tlb_on_return_to_user();
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asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
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return;
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}
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/* Flush the address out of both PCIDs. */
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/*
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* An optimization here might be to determine addresses
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* that are only kernel-mapped and only flush the kernel
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* ASID. But, userspace flushes are probably much more
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* important performance-wise.
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*
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* Make sure to do only a single invpcid when KAISER is
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* disabled and we have only a single ASID.
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*/
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if (kaiser_enabled)
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invpcid_flush_one(X86_CR3_PCID_ASID_USER, addr);
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invpcid_flush_one(X86_CR3_PCID_ASID_KERN, addr);
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}
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static inline void __flush_tlb_all(void)
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{
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__flush_tlb_global();
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/*
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* Note: if we somehow had PCID but not PGE, then this wouldn't work --
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* we'd end up flushing kernel translations for the current ASID but
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* we might fail to flush kernel translations for other cached ASIDs.
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*
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* To avoid this issue, we force PCID off if PGE is off.
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*/
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}
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static inline void __flush_tlb_one(unsigned long addr)
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{
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count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
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__flush_tlb_single(addr);
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}
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#define TLB_FLUSH_ALL -1UL
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/*
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* TLB flushing:
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*
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_others(cpumask, mm, start, end) flushes TLBs on other cpus
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*
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* ..but the i386 has somewhat limited tlb flushing capabilities,
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* and page-granular flushes are available only on i486 and up.
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*/
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#define local_flush_tlb() __flush_tlb()
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#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
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#define flush_tlb_range(vma, start, end) \
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flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
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extern void flush_tlb_all(void);
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extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
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unsigned long end, unsigned long vmflag);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
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{
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flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
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}
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void native_flush_tlb_others(const struct cpumask *cpumask,
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struct mm_struct *mm,
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unsigned long start, unsigned long end);
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#define TLBSTATE_OK 1
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#define TLBSTATE_LAZY 2
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static inline void reset_lazy_tlbstate(void)
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{
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this_cpu_write(cpu_tlbstate.state, 0);
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this_cpu_write(cpu_tlbstate.active_mm, &init_mm);
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}
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#ifndef CONFIG_PARAVIRT
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#define flush_tlb_others(mask, mm, start, end) \
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native_flush_tlb_others(mask, mm, start, end)
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#endif
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#endif /* _ASM_X86_TLBFLUSH_H */
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