362 lines
6.9 KiB
C
362 lines
6.9 KiB
C
#ifndef _ASM_X86_KVM_H
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#define _ASM_X86_KVM_H
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/*
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* KVM x86 specific structures and definitions
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*
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*/
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#include <linux/types.h>
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#include <linux/ioctl.h>
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#define DE_VECTOR 0
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#define DB_VECTOR 1
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#define BP_VECTOR 3
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#define OF_VECTOR 4
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#define BR_VECTOR 5
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#define UD_VECTOR 6
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#define NM_VECTOR 7
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#define DF_VECTOR 8
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#define TS_VECTOR 10
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#define NP_VECTOR 11
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#define SS_VECTOR 12
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#define GP_VECTOR 13
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#define PF_VECTOR 14
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#define MF_VECTOR 16
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#define AC_VECTOR 17
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#define MC_VECTOR 18
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#define XM_VECTOR 19
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#define VE_VECTOR 20
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/* Select x86 specific features in <linux/kvm.h> */
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#define __KVM_HAVE_PIT
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#define __KVM_HAVE_IOAPIC
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#define __KVM_HAVE_IRQ_LINE
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#define __KVM_HAVE_MSI
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#define __KVM_HAVE_USER_NMI
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_MSIX
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#define __KVM_HAVE_MCE
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#define __KVM_HAVE_PIT_STATE2
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#define __KVM_HAVE_XEN_HVM
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#define __KVM_HAVE_VCPU_EVENTS
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#define __KVM_HAVE_DEBUGREGS
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#define __KVM_HAVE_XSAVE
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#define __KVM_HAVE_XCRS
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#define __KVM_HAVE_READONLY_MEM
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/* Architectural interrupt line count. */
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#define KVM_NR_INTERRUPTS 256
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struct kvm_memory_alias {
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__u32 slot; /* this has a different namespace than memory slots */
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__u32 flags;
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__u64 guest_phys_addr;
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__u64 memory_size;
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__u64 target_phys_addr;
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};
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/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
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struct kvm_pic_state {
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__u8 last_irr; /* edge detection */
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__u8 irr; /* interrupt request register */
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__u8 imr; /* interrupt mask register */
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__u8 isr; /* interrupt service register */
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__u8 priority_add; /* highest irq priority */
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__u8 irq_base;
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__u8 read_reg_select;
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__u8 poll;
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__u8 special_mask;
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__u8 init_state;
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__u8 auto_eoi;
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__u8 rotate_on_auto_eoi;
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__u8 special_fully_nested_mode;
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__u8 init4; /* true if 4 byte init */
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__u8 elcr; /* PIIX edge/trigger selection */
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__u8 elcr_mask;
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};
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#define KVM_IOAPIC_NUM_PINS 24
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struct kvm_ioapic_state {
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__u64 base_address;
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__u32 ioregsel;
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__u32 id;
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__u32 irr;
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__u32 pad;
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union {
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__u64 bits;
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struct {
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__u8 vector;
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__u8 delivery_mode:3;
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__u8 dest_mode:1;
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__u8 delivery_status:1;
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__u8 polarity:1;
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__u8 remote_irr:1;
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__u8 trig_mode:1;
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__u8 mask:1;
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__u8 reserve:7;
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__u8 reserved[4];
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__u8 dest_id;
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} fields;
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} redirtbl[KVM_IOAPIC_NUM_PINS];
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};
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#define KVM_IRQCHIP_PIC_MASTER 0
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#define KVM_IRQCHIP_PIC_SLAVE 1
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#define KVM_IRQCHIP_IOAPIC 2
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#define KVM_NR_IRQCHIPS 3
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#define KVM_RUN_X86_SMM (1 << 0)
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/* for KVM_GET_REGS and KVM_SET_REGS */
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struct kvm_regs {
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/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
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__u64 rax, rbx, rcx, rdx;
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__u64 rsi, rdi, rsp, rbp;
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__u64 r8, r9, r10, r11;
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__u64 r12, r13, r14, r15;
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__u64 rip, rflags;
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};
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/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
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#define KVM_APIC_REG_SIZE 0x400
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struct kvm_lapic_state {
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char regs[KVM_APIC_REG_SIZE];
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};
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struct kvm_segment {
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__u64 base;
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__u32 limit;
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__u16 selector;
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__u8 type;
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__u8 present, dpl, db, s, l, g, avl;
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__u8 unusable;
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__u8 padding;
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};
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struct kvm_dtable {
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__u64 base;
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__u16 limit;
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__u16 padding[3];
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};
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/* for KVM_GET_SREGS and KVM_SET_SREGS */
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struct kvm_sregs {
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/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
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struct kvm_segment cs, ds, es, fs, gs, ss;
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struct kvm_segment tr, ldt;
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struct kvm_dtable gdt, idt;
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__u64 cr0, cr2, cr3, cr4, cr8;
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__u64 efer;
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__u64 apic_base;
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__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
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};
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/* for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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__u8 fpr[8][16];
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__u16 fcw;
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__u16 fsw;
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__u8 ftwx; /* in fxsave format */
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__u8 pad1;
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__u16 last_opcode;
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__u64 last_ip;
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__u64 last_dp;
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__u8 xmm[16][16];
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__u32 mxcsr;
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__u32 pad2;
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};
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struct kvm_msr_entry {
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__u32 index;
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__u32 reserved;
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__u64 data;
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};
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/* for KVM_GET_MSRS and KVM_SET_MSRS */
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struct kvm_msrs {
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__u32 nmsrs; /* number of msrs in entries */
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__u32 pad;
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struct kvm_msr_entry entries[0];
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};
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/* for KVM_GET_MSR_INDEX_LIST */
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struct kvm_msr_list {
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__u32 nmsrs; /* number of msrs in entries */
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__u32 indices[0];
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};
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struct kvm_cpuid_entry {
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__u32 function;
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__u32 eax;
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__u32 ebx;
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__u32 ecx;
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__u32 edx;
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__u32 padding;
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};
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/* for KVM_SET_CPUID */
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struct kvm_cpuid {
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__u32 nent;
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__u32 padding;
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struct kvm_cpuid_entry entries[0];
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};
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struct kvm_cpuid_entry2 {
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__u32 function;
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__u32 index;
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__u32 flags;
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__u32 eax;
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__u32 ebx;
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__u32 ecx;
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__u32 edx;
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__u32 padding[3];
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};
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#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0)
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#define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1)
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#define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2)
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/* for KVM_SET_CPUID2 */
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struct kvm_cpuid2 {
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__u32 nent;
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__u32 padding;
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struct kvm_cpuid_entry2 entries[0];
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};
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/* for KVM_GET_PIT and KVM_SET_PIT */
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struct kvm_pit_channel_state {
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__u32 count; /* can be 65536 */
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__u16 latched_count;
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__u8 count_latched;
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__u8 status_latched;
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__u8 status;
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__u8 read_state;
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__u8 write_state;
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__u8 write_latch;
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__u8 rw_mode;
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__u8 mode;
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__u8 bcd;
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__u8 gate;
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__s64 count_load_time;
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};
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struct kvm_debug_exit_arch {
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__u32 exception;
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__u32 pad;
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__u64 pc;
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__u64 dr6;
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__u64 dr7;
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};
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#define KVM_GUESTDBG_USE_SW_BP 0x00010000
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#define KVM_GUESTDBG_USE_HW_BP 0x00020000
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#define KVM_GUESTDBG_INJECT_DB 0x00040000
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#define KVM_GUESTDBG_INJECT_BP 0x00080000
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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__u64 debugreg[8];
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};
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struct kvm_pit_state {
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struct kvm_pit_channel_state channels[3];
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};
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#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
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struct kvm_pit_state2 {
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struct kvm_pit_channel_state channels[3];
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__u32 flags;
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__u32 reserved[9];
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};
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struct kvm_reinject_control {
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__u8 pit_reinject;
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__u8 reserved[31];
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};
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/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
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#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
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#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
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#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
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#define KVM_VCPUEVENT_VALID_SMM 0x00000008
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/* Interrupt shadow states */
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#define KVM_X86_SHADOW_INT_MOV_SS 0x01
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#define KVM_X86_SHADOW_INT_STI 0x02
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/* for KVM_GET/SET_VCPU_EVENTS */
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struct kvm_vcpu_events {
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struct {
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__u8 injected;
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__u8 nr;
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__u8 has_error_code;
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__u8 pad;
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__u32 error_code;
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} exception;
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struct {
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__u8 injected;
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__u8 nr;
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__u8 soft;
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__u8 shadow;
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} interrupt;
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struct {
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__u8 injected;
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__u8 pending;
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__u8 masked;
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__u8 pad;
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} nmi;
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__u32 sipi_vector;
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__u32 flags;
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struct {
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__u8 smm;
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__u8 pending;
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__u8 smm_inside_nmi;
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__u8 latched_init;
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} smi;
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__u32 reserved[9];
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};
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/* for KVM_GET/SET_DEBUGREGS */
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struct kvm_debugregs {
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__u64 db[4];
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__u64 dr6;
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__u64 dr7;
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__u64 flags;
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__u64 reserved[9];
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};
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/* for KVM_CAP_XSAVE */
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struct kvm_xsave {
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__u32 region[1024];
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};
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#define KVM_MAX_XCRS 16
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struct kvm_xcr {
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__u32 xcr;
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__u32 reserved;
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__u64 value;
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};
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struct kvm_xcrs {
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__u32 nr_xcrs;
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__u32 flags;
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struct kvm_xcr xcrs[KVM_MAX_XCRS];
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__u64 padding[16];
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};
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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#define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
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#define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
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#define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2)
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#endif /* _ASM_X86_KVM_H */
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