332 lines
8.3 KiB
C
332 lines
8.3 KiB
C
/*
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* arch/xtensa/mm/cache.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001-2006 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Joe Taylor
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* Marc Gauthier
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*
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*/
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#include <linux/init.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/bootmem.h>
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#include <linux/swap.h>
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#include <linux/pagemap.h>
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#include <asm/bootparam.h>
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#include <asm/mmu_context.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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//#define printd(x...) printk(x)
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#define printd(x...) do { } while(0)
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/*
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* Note:
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* The kernel provides one architecture bit PG_arch_1 in the page flags that
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* can be used for cache coherency.
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*
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* I$-D$ coherency.
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*
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* The Xtensa architecture doesn't keep the instruction cache coherent with
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* the data cache. We use the architecture bit to indicate if the caches
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* are coherent. The kernel clears this bit whenever a page is added to the
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* page cache. At that time, the caches might not be in sync. We, therefore,
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* define this flag as 'clean' if set.
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*
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* D-cache aliasing.
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*
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* With cache aliasing, we have to always flush the cache when pages are
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* unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
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* page.
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*
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*
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*
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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static inline void kmap_invalidate_coherent(struct page *page,
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unsigned long vaddr)
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{
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if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
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unsigned long kvaddr;
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if (!PageHighMem(page)) {
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kvaddr = (unsigned long)page_to_virt(page);
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__invalidate_dcache_page(kvaddr);
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} else {
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kvaddr = TLBTEMP_BASE_1 +
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(page_to_phys(page) & DCACHE_ALIAS_MASK);
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preempt_disable();
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__invalidate_dcache_page_alias(kvaddr,
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page_to_phys(page));
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preempt_enable();
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}
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}
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}
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static inline void *coherent_kvaddr(struct page *page, unsigned long base,
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unsigned long vaddr, unsigned long *paddr)
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{
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if (PageHighMem(page) || !DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
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*paddr = page_to_phys(page);
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return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
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} else {
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*paddr = 0;
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return page_to_virt(page);
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}
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}
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void clear_user_highpage(struct page *page, unsigned long vaddr)
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{
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unsigned long paddr;
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void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
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preempt_disable();
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kmap_invalidate_coherent(page, vaddr);
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set_bit(PG_arch_1, &page->flags);
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clear_page_alias(kvaddr, paddr);
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preempt_enable();
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}
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EXPORT_SYMBOL(clear_user_highpage);
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void copy_user_highpage(struct page *dst, struct page *src,
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unsigned long vaddr, struct vm_area_struct *vma)
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{
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unsigned long dst_paddr, src_paddr;
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void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
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&dst_paddr);
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void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
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&src_paddr);
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preempt_disable();
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kmap_invalidate_coherent(dst, vaddr);
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set_bit(PG_arch_1, &dst->flags);
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copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
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preempt_enable();
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}
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EXPORT_SYMBOL(copy_user_highpage);
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/*
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* Any time the kernel writes to a user page cache page, or it is about to
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* read from a page cache page this routine is called.
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*
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*/
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping(page);
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/*
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* If we have a mapping but the page is not mapped to user-space
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* yet, we simply mark this page dirty and defer flushing the
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* caches until update_mmu().
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*/
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if (mapping && !mapping_mapped(mapping)) {
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if (!test_bit(PG_arch_1, &page->flags))
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set_bit(PG_arch_1, &page->flags);
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return;
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} else {
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unsigned long phys = page_to_phys(page);
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unsigned long temp = page->index << PAGE_SHIFT;
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unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
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unsigned long virt;
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/*
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* Flush the page in kernel space and user space.
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* Note that we can omit that step if aliasing is not
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* an issue, but we do have to synchronize I$ and D$
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* if we have a mapping.
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*/
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if (!alias && !mapping)
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return;
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preempt_disable();
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virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(virt, phys);
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virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
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if (alias)
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__flush_invalidate_dcache_page_alias(virt, phys);
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if (mapping)
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__invalidate_icache_page_alias(virt, phys);
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preempt_enable();
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}
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/* There shouldn't be an entry in the cache for this page anymore. */
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}
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EXPORT_SYMBOL(flush_dcache_page);
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/*
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* For now, flush the whole cache. FIXME??
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*/
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void local_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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__flush_invalidate_dcache_all();
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__invalidate_icache_all();
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}
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EXPORT_SYMBOL(local_flush_cache_range);
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/*
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* Remove any entry in the cache for this page.
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*
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* Note that this function is only called for user pages, so use the
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* alias versions of the cache flush functions.
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*/
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void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
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unsigned long pfn)
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{
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/* Note that we have to use the 'alias' address to avoid multi-hit */
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unsigned long phys = page_to_phys(pfn_to_page(pfn));
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unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);
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preempt_disable();
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__flush_invalidate_dcache_page_alias(virt, phys);
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__invalidate_icache_page_alias(virt, phys);
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preempt_enable();
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}
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EXPORT_SYMBOL(local_flush_cache_page);
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#endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
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void
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update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
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{
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unsigned long pfn = pte_pfn(*ptep);
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struct page *page;
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if (!pfn_valid(pfn))
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return;
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page = pfn_to_page(pfn);
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/* Invalidate old entry in TLBs */
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flush_tlb_page(vma, addr);
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
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unsigned long phys = page_to_phys(page);
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unsigned long tmp;
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preempt_disable();
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tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(tmp, phys);
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tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(tmp, phys);
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__invalidate_icache_page_alias(tmp, phys);
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preempt_enable();
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clear_bit(PG_arch_1, &page->flags);
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}
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#else
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if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
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&& (vma->vm_flags & VM_EXEC) != 0) {
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unsigned long paddr = (unsigned long)kmap_atomic(page);
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__flush_dcache_page(paddr);
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__invalidate_icache_page(paddr);
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set_bit(PG_arch_1, &page->flags);
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kunmap_atomic((void *)paddr);
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}
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#endif
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}
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/*
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* access_process_vm() has called get_user_pages(), which has done a
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* flush_dcache_page() on the page.
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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unsigned long phys = page_to_phys(page);
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unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
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/* Flush and invalidate user page if aliased. */
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if (alias) {
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unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
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preempt_disable();
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__flush_invalidate_dcache_page_alias(t, phys);
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preempt_enable();
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}
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/* Copy data */
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memcpy(dst, src, len);
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/*
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* Flush and invalidate kernel page if aliased and synchronize
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* data and instruction caches for executable pages.
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*/
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if (alias) {
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unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
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preempt_disable();
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__flush_invalidate_dcache_range((unsigned long) dst, len);
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if ((vma->vm_flags & VM_EXEC) != 0)
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__invalidate_icache_page_alias(t, phys);
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preempt_enable();
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} else if ((vma->vm_flags & VM_EXEC) != 0) {
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__flush_dcache_range((unsigned long)dst,len);
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__invalidate_icache_range((unsigned long) dst, len);
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}
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}
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extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long vaddr, void *dst, const void *src,
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unsigned long len)
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{
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unsigned long phys = page_to_phys(page);
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unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
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/*
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* Flush user page if aliased.
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* (Note: a simply flush would be sufficient)
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*/
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if (alias) {
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unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
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preempt_disable();
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__flush_invalidate_dcache_page_alias(t, phys);
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preempt_enable();
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}
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memcpy(dst, src, len);
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}
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#endif
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