239 lines
6.1 KiB
C
239 lines
6.1 KiB
C
/*
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* Copyright (C) 2015 Xilinx, Inc.
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* CEVA AHCI SATA platform driver
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*
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/ahci_platform.h>
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#include <linux/kernel.h>
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#include <linux/libata.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "ahci.h"
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/* Vendor Specific Register Offsets */
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#define AHCI_VEND_PCFG 0xA4
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#define AHCI_VEND_PPCFG 0xA8
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#define AHCI_VEND_PP2C 0xAC
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#define AHCI_VEND_PP3C 0xB0
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#define AHCI_VEND_PP4C 0xB4
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#define AHCI_VEND_PP5C 0xB8
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#define AHCI_VEND_PAXIC 0xC0
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#define AHCI_VEND_PTC 0xC8
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/* Vendor Specific Register bit definitions */
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#define PAXIC_ADBW_BW64 0x1
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#define PAXIC_MAWIDD (1 << 8)
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#define PAXIC_MARIDD (1 << 16)
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#define PAXIC_OTL (0x4 << 20)
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#define PCFG_TPSS_VAL (0x32 << 16)
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#define PCFG_TPRS_VAL (0x2 << 12)
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#define PCFG_PAD_VAL 0x2
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#define PPCFG_TTA 0x1FFFE
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#define PPCFG_PSSO_EN (1 << 28)
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#define PPCFG_PSS_EN (1 << 29)
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#define PPCFG_ESDF_EN (1 << 31)
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#define PP2C_CIBGMN 0x0F
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#define PP2C_CIBGMX (0x25 << 8)
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#define PP2C_CIBGN (0x18 << 16)
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#define PP2C_CINMP (0x29 << 24)
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#define PP3C_CWBGMN 0x04
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#define PP3C_CWBGMX (0x0B << 8)
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#define PP3C_CWBGN (0x08 << 16)
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#define PP3C_CWNMP (0x0F << 24)
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#define PP4C_BMX 0x0a
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#define PP4C_BNM (0x08 << 8)
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#define PP4C_SFD (0x4a << 16)
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#define PP4C_PTST (0x06 << 24)
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#define PP5C_RIT 0x60216
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#define PP5C_RCT (0x7f0 << 20)
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#define PTC_RX_WM_VAL 0x40
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#define PTC_RSVD (1 << 27)
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#define PORT0_BASE 0x100
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#define PORT1_BASE 0x180
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/* Port Control Register Bit Definitions */
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#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
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#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
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#define PORT_SCTL_IPM (0x3 << 8)
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#define PORT_BASE 0x100
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#define PORT_OFFSET 0x80
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#define NR_PORTS 2
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#define DRV_NAME "ahci-ceva"
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#define CEVA_FLAG_BROKEN_GEN2 1
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struct ceva_ahci_priv {
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struct platform_device *ahci_pdev;
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int flags;
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};
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static struct ata_port_operations ahci_ceva_ops = {
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.inherits = &ahci_platform_ops,
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};
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static const struct ata_port_info ahci_ceva_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_ceva_ops,
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};
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static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
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{
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void __iomem *mmio = hpriv->mmio;
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struct ceva_ahci_priv *cevapriv = hpriv->plat_data;
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u32 tmp;
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int i;
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/*
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* AXI Data bus width to 64
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* Set Mem Addr Read, Write ID for data transfers
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* Transfer limit to 72 DWord
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*/
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tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
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writel(tmp, mmio + AHCI_VEND_PAXIC);
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/* Set AHCI Enable */
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tmp = readl(mmio + HOST_CTL);
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tmp |= HOST_AHCI_EN;
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writel(tmp, mmio + HOST_CTL);
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for (i = 0; i < NR_PORTS; i++) {
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/* TPSS TPRS scalars, CISE and Port Addr */
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tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
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writel(tmp, mmio + AHCI_VEND_PCFG);
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/* Port Phy Cfg register enables */
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tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
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writel(tmp, mmio + AHCI_VEND_PPCFG);
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/* Phy Control OOB timing parameters COMINIT */
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tmp = PP2C_CIBGMN | PP2C_CIBGMX | PP2C_CIBGN | PP2C_CINMP;
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writel(tmp, mmio + AHCI_VEND_PP2C);
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/* Phy Control OOB timing parameters COMWAKE */
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tmp = PP3C_CWBGMN | PP3C_CWBGMX | PP3C_CWBGN | PP3C_CWNMP;
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writel(tmp, mmio + AHCI_VEND_PP3C);
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/* Phy Control Burst timing setting */
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tmp = PP4C_BMX | PP4C_BNM | PP4C_SFD | PP4C_PTST;
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writel(tmp, mmio + AHCI_VEND_PP4C);
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/* Rate Change Timer and Retry Interval Timer setting */
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tmp = PP5C_RIT | PP5C_RCT;
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writel(tmp, mmio + AHCI_VEND_PP5C);
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/* Rx Watermark setting */
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tmp = PTC_RX_WM_VAL | PTC_RSVD;
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writel(tmp, mmio + AHCI_VEND_PTC);
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/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
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tmp = PORT_SCTL_SPD_GEN2 | PORT_SCTL_IPM;
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if (cevapriv->flags & CEVA_FLAG_BROKEN_GEN2)
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tmp = PORT_SCTL_SPD_GEN1 | PORT_SCTL_IPM;
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writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
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}
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}
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static struct scsi_host_template ahci_platform_sht = {
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AHCI_SHT(DRV_NAME),
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};
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static int ceva_ahci_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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struct ceva_ahci_priv *cevapriv;
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int rc;
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cevapriv = devm_kzalloc(dev, sizeof(*cevapriv), GFP_KERNEL);
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if (!cevapriv)
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return -ENOMEM;
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cevapriv->ahci_pdev = pdev;
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hpriv = ahci_platform_get_resources(pdev);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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if (of_property_read_bool(np, "ceva,broken-gen2"))
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cevapriv->flags = CEVA_FLAG_BROKEN_GEN2;
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hpriv->plat_data = cevapriv;
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/* CEVA specific initialization */
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ahci_ceva_setup(hpriv);
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rc = ahci_platform_init_host(pdev, hpriv, &ahci_ceva_port_info,
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&ahci_platform_sht);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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static int __maybe_unused ceva_ahci_suspend(struct device *dev)
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{
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return ahci_platform_suspend_host(dev);
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}
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static int __maybe_unused ceva_ahci_resume(struct device *dev)
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{
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return ahci_platform_resume_host(dev);
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}
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static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
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static const struct of_device_id ceva_ahci_of_match[] = {
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{ .compatible = "ceva,ahci-1v84" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ceva_ahci_of_match);
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static struct platform_driver ceva_ahci_driver = {
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.probe = ceva_ahci_probe,
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.remove = ata_platform_remove_one,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = ceva_ahci_of_match,
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.pm = &ahci_ceva_pm_ops,
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},
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};
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module_platform_driver(ceva_ahci_driver);
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MODULE_DESCRIPTION("CEVA AHCI SATA platform driver");
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MODULE_AUTHOR("Xilinx Inc.");
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MODULE_LICENSE("GPL v2");
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