554 lines
13 KiB
C
554 lines
13 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef __MBCS_H__
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#define __MBCS_H__
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/*
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* General macros
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*/
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#define MB (1024*1024)
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#define MB2 (2*MB)
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#define MB4 (4*MB)
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#define MB6 (6*MB)
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/*
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* Offsets and masks
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*/
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#define MBCS_CM_ID 0x0000 /* Identification */
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#define MBCS_CM_STATUS 0x0008 /* Status */
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#define MBCS_CM_ERROR_DETAIL1 0x0010 /* Error Detail1 */
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#define MBCS_CM_ERROR_DETAIL2 0x0018 /* Error Detail2 */
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#define MBCS_CM_CONTROL 0x0020 /* Control */
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#define MBCS_CM_REQ_TOUT 0x0028 /* Request Time-out */
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#define MBCS_CM_ERR_INT_DEST 0x0038 /* Error Interrupt Destination */
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#define MBCS_CM_TARG_FL 0x0050 /* Target Flush */
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#define MBCS_CM_ERR_STAT 0x0060 /* Error Status */
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#define MBCS_CM_CLR_ERR_STAT 0x0068 /* Clear Error Status */
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#define MBCS_CM_ERR_INT_EN 0x0070 /* Error Interrupt Enable */
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#define MBCS_RD_DMA_SYS_ADDR 0x0100 /* Read DMA System Address */
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#define MBCS_RD_DMA_LOC_ADDR 0x0108 /* Read DMA Local Address */
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#define MBCS_RD_DMA_CTRL 0x0110 /* Read DMA Control */
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#define MBCS_RD_DMA_AMO_DEST 0x0118 /* Read DMA AMO Destination */
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#define MBCS_RD_DMA_INT_DEST 0x0120 /* Read DMA Interrupt Destination */
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#define MBCS_RD_DMA_AUX_STAT 0x0130 /* Read DMA Auxiliary Status */
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#define MBCS_WR_DMA_SYS_ADDR 0x0200 /* Write DMA System Address */
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#define MBCS_WR_DMA_LOC_ADDR 0x0208 /* Write DMA Local Address */
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#define MBCS_WR_DMA_CTRL 0x0210 /* Write DMA Control */
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#define MBCS_WR_DMA_AMO_DEST 0x0218 /* Write DMA AMO Destination */
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#define MBCS_WR_DMA_INT_DEST 0x0220 /* Write DMA Interrupt Destination */
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#define MBCS_WR_DMA_AUX_STAT 0x0230 /* Write DMA Auxiliary Status */
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#define MBCS_ALG_AMO_DEST 0x0300 /* Algorithm AMO Destination */
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#define MBCS_ALG_INT_DEST 0x0308 /* Algorithm Interrupt Destination */
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#define MBCS_ALG_OFFSETS 0x0310
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#define MBCS_ALG_STEP 0x0318 /* Algorithm Step */
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#define MBCS_GSCR_START 0x0000000
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#define MBCS_DEBUG_START 0x0100000
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#define MBCS_RAM0_START 0x0200000
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#define MBCS_RAM1_START 0x0400000
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#define MBCS_RAM2_START 0x0600000
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#define MBCS_CM_CONTROL_REQ_TOUT_MASK 0x0000000000ffffffUL
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//#define PIO_BASE_ADDR_BASE_OFFSET_MASK 0x00fffffffff00000UL
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#define MBCS_SRAM_SIZE (1024*1024)
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#define MBCS_CACHELINE_SIZE 128
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/*
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* MMR get's and put's
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*/
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#define MBCS_MMR_ADDR(mmr_base, offset)((uint64_t *)(mmr_base + offset))
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#define MBCS_MMR_SET(mmr_base, offset, value) { \
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uint64_t *mbcs_mmr_set_u64p, readback; \
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mbcs_mmr_set_u64p = (uint64_t *)(mmr_base + offset); \
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*mbcs_mmr_set_u64p = value; \
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readback = *mbcs_mmr_set_u64p; \
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}
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#define MBCS_MMR_GET(mmr_base, offset) *(uint64_t *)(mmr_base + offset)
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#define MBCS_MMR_ZERO(mmr_base, offset) MBCS_MMR_SET(mmr_base, offset, 0)
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/*
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* MBCS mmr structures
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*/
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union cm_id {
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uint64_t cm_id_reg;
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struct {
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uint64_t always_one:1, // 0
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mfg_id:11, // 11:1
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part_num:16, // 27:12
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bitstream_rev:8, // 35:28
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:28; // 63:36
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};
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};
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union cm_status {
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uint64_t cm_status_reg;
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struct {
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uint64_t pending_reads:8, // 7:0
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pending_writes:8, // 15:8
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ice_rsp_credits:8, // 23:16
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ice_req_credits:8, // 31:24
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cm_req_credits:8, // 39:32
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:1, // 40
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rd_dma_in_progress:1, // 41
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rd_dma_done:1, // 42
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:1, // 43
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wr_dma_in_progress:1, // 44
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wr_dma_done:1, // 45
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alg_waiting:1, // 46
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alg_pipe_running:1, // 47
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alg_done:1, // 48
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:3, // 51:49
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pending_int_reqs:8, // 59:52
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:3, // 62:60
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alg_half_speed_sel:1; // 63
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};
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};
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union cm_error_detail1 {
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uint64_t cm_error_detail1_reg;
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struct {
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uint64_t packet_type:4, // 3:0
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source_id:2, // 5:4
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data_size:2, // 7:6
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tnum:8, // 15:8
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byte_enable:8, // 23:16
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gfx_cred:8, // 31:24
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read_type:2, // 33:32
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pio_or_memory:1, // 34
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head_cw_error:1, // 35
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:12, // 47:36
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head_error_bit:1, // 48
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data_error_bit:1, // 49
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:13, // 62:50
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valid:1; // 63
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};
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};
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union cm_error_detail2 {
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uint64_t cm_error_detail2_reg;
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struct {
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uint64_t address:56, // 55:0
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:8; // 63:56
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};
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};
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union cm_control {
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uint64_t cm_control_reg;
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struct {
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uint64_t cm_id:2, // 1:0
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:2, // 3:2
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max_trans:5, // 8:4
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:3, // 11:9
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address_mode:1, // 12
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:7, // 19:13
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credit_limit:8, // 27:20
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:5, // 32:28
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rearm_stat_regs:1, // 33
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prescalar_byp:1, // 34
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force_gap_war:1, // 35
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rd_dma_go:1, // 36
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wr_dma_go:1, // 37
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alg_go:1, // 38
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rd_dma_clr:1, // 39
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wr_dma_clr:1, // 40
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alg_clr:1, // 41
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:2, // 43:42
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alg_wait_step:1, // 44
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alg_done_amo_en:1, // 45
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alg_done_int_en:1, // 46
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:1, // 47
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alg_sram0_locked:1, // 48
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alg_sram1_locked:1, // 49
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alg_sram2_locked:1, // 50
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alg_done_clr:1, // 51
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:12; // 63:52
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};
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};
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union cm_req_timeout {
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uint64_t cm_req_timeout_reg;
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struct {
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uint64_t time_out:24, // 23:0
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:40; // 63:24
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};
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};
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union intr_dest {
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uint64_t intr_dest_reg;
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struct {
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uint64_t address:56, // 55:0
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int_vector:8; // 63:56
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};
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};
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union cm_error_status {
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uint64_t cm_error_status_reg;
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struct {
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uint64_t ecc_sbe:1, // 0
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ecc_mbe:1, // 1
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unsupported_req:1, // 2
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unexpected_rsp:1, // 3
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bad_length:1, // 4
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bad_datavalid:1, // 5
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buffer_overflow:1, // 6
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request_timeout:1, // 7
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:8, // 15:8
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head_inv_data_size:1, // 16
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rsp_pactype_inv:1, // 17
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head_sb_err:1, // 18
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missing_head:1, // 19
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head_inv_rd_type:1, // 20
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head_cmd_err_bit:1, // 21
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req_addr_align_inv:1, // 22
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pio_req_addr_inv:1, // 23
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req_range_dsize_inv:1, // 24
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early_term:1, // 25
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early_tail:1, // 26
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missing_tail:1, // 27
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data_flit_sb_err:1, // 28
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cm2hcm_req_cred_of:1, // 29
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cm2hcm_rsp_cred_of:1, // 30
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rx_bad_didn:1, // 31
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rd_dma_err_rsp:1, // 32
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rd_dma_tnum_tout:1, // 33
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rd_dma_multi_tnum_tou:1, // 34
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wr_dma_err_rsp:1, // 35
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wr_dma_tnum_tout:1, // 36
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wr_dma_multi_tnum_tou:1, // 37
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alg_data_overflow:1, // 38
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alg_data_underflow:1, // 39
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ram0_access_conflict:1, // 40
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ram1_access_conflict:1, // 41
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ram2_access_conflict:1, // 42
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ram0_perr:1, // 43
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ram1_perr:1, // 44
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ram2_perr:1, // 45
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int_gen_rsp_err:1, // 46
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int_gen_tnum_tout:1, // 47
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rd_dma_prog_err:1, // 48
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wr_dma_prog_err:1, // 49
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:14; // 63:50
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};
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};
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union cm_clr_error_status {
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uint64_t cm_clr_error_status_reg;
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struct {
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uint64_t clr_ecc_sbe:1, // 0
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clr_ecc_mbe:1, // 1
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clr_unsupported_req:1, // 2
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clr_unexpected_rsp:1, // 3
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clr_bad_length:1, // 4
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clr_bad_datavalid:1, // 5
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clr_buffer_overflow:1, // 6
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clr_request_timeout:1, // 7
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:8, // 15:8
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clr_head_inv_data_siz:1, // 16
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clr_rsp_pactype_inv:1, // 17
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clr_head_sb_err:1, // 18
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clr_missing_head:1, // 19
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clr_head_inv_rd_type:1, // 20
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clr_head_cmd_err_bit:1, // 21
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clr_req_addr_align_in:1, // 22
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clr_pio_req_addr_inv:1, // 23
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clr_req_range_dsize_i:1, // 24
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clr_early_term:1, // 25
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clr_early_tail:1, // 26
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clr_missing_tail:1, // 27
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clr_data_flit_sb_err:1, // 28
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clr_cm2hcm_req_cred_o:1, // 29
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clr_cm2hcm_rsp_cred_o:1, // 30
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clr_rx_bad_didn:1, // 31
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clr_rd_dma_err_rsp:1, // 32
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clr_rd_dma_tnum_tout:1, // 33
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clr_rd_dma_multi_tnum:1, // 34
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clr_wr_dma_err_rsp:1, // 35
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clr_wr_dma_tnum_tout:1, // 36
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clr_wr_dma_multi_tnum:1, // 37
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clr_alg_data_overflow:1, // 38
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clr_alg_data_underflo:1, // 39
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clr_ram0_access_confl:1, // 40
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clr_ram1_access_confl:1, // 41
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clr_ram2_access_confl:1, // 42
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clr_ram0_perr:1, // 43
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clr_ram1_perr:1, // 44
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clr_ram2_perr:1, // 45
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clr_int_gen_rsp_err:1, // 46
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clr_int_gen_tnum_tout:1, // 47
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clr_rd_dma_prog_err:1, // 48
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clr_wr_dma_prog_err:1, // 49
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:14; // 63:50
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};
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};
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union cm_error_intr_enable {
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uint64_t cm_error_intr_enable_reg;
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struct {
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uint64_t int_en_ecc_sbe:1, // 0
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int_en_ecc_mbe:1, // 1
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int_en_unsupported_re:1, // 2
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int_en_unexpected_rsp:1, // 3
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int_en_bad_length:1, // 4
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int_en_bad_datavalid:1, // 5
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int_en_buffer_overflo:1, // 6
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int_en_request_timeou:1, // 7
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:8, // 15:8
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int_en_head_inv_data_:1, // 16
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int_en_rsp_pactype_in:1, // 17
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int_en_head_sb_err:1, // 18
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int_en_missing_head:1, // 19
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int_en_head_inv_rd_ty:1, // 20
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int_en_head_cmd_err_b:1, // 21
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int_en_req_addr_align:1, // 22
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int_en_pio_req_addr_i:1, // 23
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int_en_req_range_dsiz:1, // 24
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int_en_early_term:1, // 25
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int_en_early_tail:1, // 26
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int_en_missing_tail:1, // 27
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int_en_data_flit_sb_e:1, // 28
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int_en_cm2hcm_req_cre:1, // 29
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int_en_cm2hcm_rsp_cre:1, // 30
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int_en_rx_bad_didn:1, // 31
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int_en_rd_dma_err_rsp:1, // 32
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int_en_rd_dma_tnum_to:1, // 33
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int_en_rd_dma_multi_t:1, // 34
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int_en_wr_dma_err_rsp:1, // 35
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int_en_wr_dma_tnum_to:1, // 36
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int_en_wr_dma_multi_t:1, // 37
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int_en_alg_data_overf:1, // 38
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int_en_alg_data_under:1, // 39
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int_en_ram0_access_co:1, // 40
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int_en_ram1_access_co:1, // 41
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int_en_ram2_access_co:1, // 42
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int_en_ram0_perr:1, // 43
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int_en_ram1_perr:1, // 44
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int_en_ram2_perr:1, // 45
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int_en_int_gen_rsp_er:1, // 46
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int_en_int_gen_tnum_t:1, // 47
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int_en_rd_dma_prog_er:1, // 48
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int_en_wr_dma_prog_er:1, // 49
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:14; // 63:50
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};
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};
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struct cm_mmr {
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union cm_id id;
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union cm_status status;
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union cm_error_detail1 err_detail1;
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union cm_error_detail2 err_detail2;
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union cm_control control;
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union cm_req_timeout req_timeout;
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uint64_t reserved1[1];
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union intr_dest int_dest;
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uint64_t reserved2[2];
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uint64_t targ_flush;
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uint64_t reserved3[1];
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union cm_error_status err_status;
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union cm_clr_error_status clr_err_status;
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union cm_error_intr_enable int_enable;
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};
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union dma_hostaddr {
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uint64_t dma_hostaddr_reg;
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struct {
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uint64_t dma_sys_addr:56, // 55:0
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:8; // 63:56
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};
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};
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union dma_localaddr {
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uint64_t dma_localaddr_reg;
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struct {
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uint64_t dma_ram_addr:21, // 20:0
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dma_ram_sel:2, // 22:21
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:41; // 63:23
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};
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};
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union dma_control {
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uint64_t dma_control_reg;
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struct {
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uint64_t dma_op_length:16, // 15:0
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:18, // 33:16
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done_amo_en:1, // 34
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done_int_en:1, // 35
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:1, // 36
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pio_mem_n:1, // 37
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:26; // 63:38
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};
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};
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union dma_amo_dest {
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uint64_t dma_amo_dest_reg;
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struct {
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uint64_t dma_amo_sys_addr:56, // 55:0
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dma_amo_mod_type:3, // 58:56
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:5; // 63:59
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};
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};
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union rdma_aux_status {
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uint64_t rdma_aux_status_reg;
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struct {
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uint64_t op_num_pacs_left:17, // 16:0
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:5, // 21:17
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lrsp_buff_empty:1, // 22
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:17, // 39:23
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pending_reqs_left:6, // 45:40
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:18; // 63:46
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};
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};
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struct rdma_mmr {
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union dma_hostaddr host_addr;
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union dma_localaddr local_addr;
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union dma_control control;
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union dma_amo_dest amo_dest;
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union intr_dest intr_dest;
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union rdma_aux_status aux_status;
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};
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union wdma_aux_status {
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uint64_t wdma_aux_status_reg;
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struct {
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uint64_t op_num_pacs_left:17, // 16:0
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:4, // 20:17
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lreq_buff_empty:1, // 21
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:18, // 39:22
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pending_reqs_left:6, // 45:40
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:18; // 63:46
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};
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};
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struct wdma_mmr {
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union dma_hostaddr host_addr;
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union dma_localaddr local_addr;
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union dma_control control;
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union dma_amo_dest amo_dest;
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union intr_dest intr_dest;
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union wdma_aux_status aux_status;
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};
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union algo_step {
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uint64_t algo_step_reg;
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struct {
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uint64_t alg_step_cnt:16, // 15:0
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:48; // 63:16
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};
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};
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struct algo_mmr {
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union dma_amo_dest amo_dest;
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union intr_dest intr_dest;
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union {
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uint64_t algo_offset_reg;
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struct {
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uint64_t sram0_offset:7, // 6:0
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reserved0:1, // 7
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sram1_offset:7, // 14:8
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reserved1:1, // 15
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sram2_offset:7, // 22:16
|
|
reserved2:14; // 63:23
|
|
};
|
|
} sram_offset;
|
|
union algo_step step;
|
|
};
|
|
|
|
struct mbcs_mmr {
|
|
struct cm_mmr cm;
|
|
uint64_t reserved1[17];
|
|
struct rdma_mmr rdDma;
|
|
uint64_t reserved2[25];
|
|
struct wdma_mmr wrDma;
|
|
uint64_t reserved3[25];
|
|
struct algo_mmr algo;
|
|
uint64_t reserved4[156];
|
|
};
|
|
|
|
/*
|
|
* defines
|
|
*/
|
|
#define DEVICE_NAME "mbcs"
|
|
#define MBCS_PART_NUM 0xfff0
|
|
#define MBCS_PART_NUM_ALG0 0xf001
|
|
#define MBCS_MFG_NUM 0x1
|
|
|
|
struct algoblock {
|
|
uint64_t amoHostDest;
|
|
uint64_t amoModType;
|
|
uint64_t intrHostDest;
|
|
uint64_t intrVector;
|
|
uint64_t algoStepCount;
|
|
};
|
|
|
|
struct getdma {
|
|
uint64_t hostAddr;
|
|
uint64_t localAddr;
|
|
uint64_t bytes;
|
|
uint64_t DoneAmoEnable;
|
|
uint64_t DoneIntEnable;
|
|
uint64_t peerIO;
|
|
uint64_t amoHostDest;
|
|
uint64_t amoModType;
|
|
uint64_t intrHostDest;
|
|
uint64_t intrVector;
|
|
};
|
|
|
|
struct putdma {
|
|
uint64_t hostAddr;
|
|
uint64_t localAddr;
|
|
uint64_t bytes;
|
|
uint64_t DoneAmoEnable;
|
|
uint64_t DoneIntEnable;
|
|
uint64_t peerIO;
|
|
uint64_t amoHostDest;
|
|
uint64_t amoModType;
|
|
uint64_t intrHostDest;
|
|
uint64_t intrVector;
|
|
};
|
|
|
|
struct mbcs_soft {
|
|
struct list_head list;
|
|
struct cx_dev *cxdev;
|
|
int major;
|
|
int nasid;
|
|
void *mmr_base;
|
|
wait_queue_head_t dmawrite_queue;
|
|
wait_queue_head_t dmaread_queue;
|
|
wait_queue_head_t algo_queue;
|
|
struct sn_irq_info *get_sn_irq;
|
|
struct sn_irq_info *put_sn_irq;
|
|
struct sn_irq_info *algo_sn_irq;
|
|
struct getdma getdma;
|
|
struct putdma putdma;
|
|
struct algoblock algo;
|
|
uint64_t gscr_addr; // pio addr
|
|
uint64_t ram0_addr; // pio addr
|
|
uint64_t ram1_addr; // pio addr
|
|
uint64_t ram2_addr; // pio addr
|
|
uint64_t debug_addr; // pio addr
|
|
atomic_t dmawrite_done;
|
|
atomic_t dmaread_done;
|
|
atomic_t algo_done;
|
|
struct mutex dmawritelock;
|
|
struct mutex dmareadlock;
|
|
struct mutex algolock;
|
|
};
|
|
|
|
static int mbcs_open(struct inode *ip, struct file *fp);
|
|
static ssize_t mbcs_sram_read(struct file *fp, char __user *buf, size_t len,
|
|
loff_t * off);
|
|
static ssize_t mbcs_sram_write(struct file *fp, const char __user *buf, size_t len,
|
|
loff_t * off);
|
|
static loff_t mbcs_sram_llseek(struct file *filp, loff_t off, int whence);
|
|
static int mbcs_gscr_mmap(struct file *fp, struct vm_area_struct *vma);
|
|
|
|
#endif // __MBCS_H__
|