449 lines
12 KiB
C
449 lines
12 KiB
C
/*
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* Marvell Armada 37xx SoC Peripheral clocks
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*
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* Copyright (C) 2016 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2 or later. This program is licensed "as is"
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* without any warranty of any kind, whether express or implied.
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*
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* Most of the peripheral clocks can be modelled like this:
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* _____ _______ _______
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* TBG-A-P --| | | | | | ______
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* TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
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* TBG-A-S --| | | | | | |______|
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* TBG-B-S --|_____| |_______| |_______|
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*
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* However some clocks may use only one or two block or and use the
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* xtal clock as parent.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define TBG_SEL 0x0
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#define DIV_SEL0 0x4
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#define DIV_SEL1 0x8
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#define DIV_SEL2 0xC
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#define CLK_SEL 0x10
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#define CLK_DIS 0x14
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struct clk_periph_driver_data {
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struct clk_hw_onecell_data *hw_data;
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spinlock_t lock;
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};
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struct clk_double_div {
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struct clk_hw hw;
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void __iomem *reg1;
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u8 shift1;
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void __iomem *reg2;
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u8 shift2;
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};
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#define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
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struct clk_periph_data {
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const char *name;
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const char * const *parent_names;
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int num_parents;
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struct clk_hw *mux_hw;
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struct clk_hw *rate_hw;
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struct clk_hw *gate_hw;
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bool is_double_div;
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};
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static const struct clk_div_table clk_table6[] = {
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{ .val = 1, .div = 1, },
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{ .val = 2, .div = 2, },
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{ .val = 3, .div = 3, },
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{ .val = 4, .div = 4, },
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{ .val = 5, .div = 5, },
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{ .val = 6, .div = 6, },
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{ .val = 0, .div = 0, }, /* last entry */
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};
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static const struct clk_div_table clk_table1[] = {
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{ .val = 0, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 0, .div = 0, }, /* last entry */
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};
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static const struct clk_div_table clk_table2[] = {
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{ .val = 0, .div = 2, },
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{ .val = 1, .div = 4, },
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{ .val = 0, .div = 0, }, /* last entry */
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};
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static const struct clk_ops clk_double_div_ops;
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#define PERIPH_GATE(_name, _bit) \
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struct clk_gate gate_##_name = { \
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.reg = (void *)CLK_DIS, \
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.bit_idx = _bit, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_gate_ops, \
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} \
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};
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#define PERIPH_MUX(_name, _shift) \
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struct clk_mux mux_##_name = { \
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.reg = (void *)TBG_SEL, \
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.shift = _shift, \
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.mask = 3, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_mux_ro_ops, \
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} \
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};
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#define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \
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struct clk_double_div rate_##_name = { \
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.reg1 = (void *)_reg1, \
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.reg2 = (void *)_reg2, \
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.shift1 = _shift1, \
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.shift2 = _shift2, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_double_div_ops, \
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} \
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};
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#define PERIPH_DIV(_name, _reg, _shift, _table) \
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struct clk_divider rate_##_name = { \
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.reg = (void *)_reg, \
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.table = _table, \
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.shift = _shift, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_divider_ro_ops, \
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} \
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};
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#define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
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static PERIPH_GATE(_name, _bit); \
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static PERIPH_MUX(_name, _shift); \
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static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
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#define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \
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static PERIPH_GATE(_name, _bit); \
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static PERIPH_MUX(_name, _shift); \
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static PERIPH_DIV(_name, _reg, _shift1, _table);
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#define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \
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static PERIPH_GATE(_name, _bit); \
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static PERIPH_DIV(_name, _reg, _shift, _table);
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#define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \
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static PERIPH_MUX(_name, _shift); \
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static PERIPH_DIV(_name, _reg, _shift_div, _table);
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#define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
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static PERIPH_MUX(_name, _shift); \
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static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
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#define REF_CLK_FULL(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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.mux_hw = &mux_##_name.hw, \
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.gate_hw = &gate_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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}
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#define REF_CLK_FULL_DD(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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.mux_hw = &mux_##_name.hw, \
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.gate_hw = &gate_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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.is_double_div = true, \
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}
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#define REF_CLK_GATE(_name, _parent_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ _parent_name}, \
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.num_parents = 1, \
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.gate_hw = &gate_##_name.hw, \
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}
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#define REF_CLK_GATE_DIV(_name, _parent_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ _parent_name}, \
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.num_parents = 1, \
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.gate_hw = &gate_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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}
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#define REF_CLK_MUX_DIV(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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.mux_hw = &mux_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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}
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#define REF_CLK_MUX_DD(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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.mux_hw = &mux_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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.is_double_div = true, \
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}
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/* NB periph clocks */
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PERIPH_CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13);
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PERIPH_CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7);
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PERIPH_CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0);
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PERIPH_CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6);
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PERIPH_CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12);
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PERIPH_CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, clk_table6);
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static PERIPH_GATE(avs, 11);
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PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0);
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PERIPH_CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24);
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static PERIPH_GATE(i2c_2, 16);
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static PERIPH_GATE(i2c_1, 17);
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PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2);
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PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
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PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
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PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
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PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
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PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6);
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static struct clk_periph_data data_nb[] ={
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REF_CLK_FULL_DD(mmc),
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REF_CLK_FULL_DD(sata_host),
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REF_CLK_FULL_DD(sec_at),
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REF_CLK_FULL_DD(sec_dap),
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REF_CLK_FULL_DD(tscem),
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REF_CLK_FULL(tscem_tmx),
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REF_CLK_GATE(avs, "xtal"),
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REF_CLK_FULL_DD(sqf),
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REF_CLK_FULL_DD(pwm),
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REF_CLK_GATE(i2c_2, "xtal"),
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REF_CLK_GATE(i2c_1, "xtal"),
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REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"),
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REF_CLK_FULL_DD(ddr_fclk),
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REF_CLK_FULL(trace),
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REF_CLK_FULL(counter),
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REF_CLK_FULL_DD(eip97),
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REF_CLK_MUX_DIV(cpu),
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{ },
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};
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/* SB periph clocks */
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PERIPH_CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9);
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PERIPH_CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21);
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PERIPH_CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9);
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static PERIPH_GATE(gbe1_50, 0);
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static PERIPH_GATE(gbe0_50, 1);
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static PERIPH_GATE(gbe1_125, 2);
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static PERIPH_GATE(gbe0_125, 3);
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PERIPH_CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, clk_table1);
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PERIPH_CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, clk_table1);
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PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
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PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
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PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
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PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
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static struct clk_periph_data data_sb[] = {
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REF_CLK_MUX_DD(gbe_50),
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REF_CLK_MUX_DD(gbe_core),
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REF_CLK_MUX_DD(gbe_125),
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REF_CLK_GATE(gbe1_50, "gbe_50"),
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REF_CLK_GATE(gbe0_50, "gbe_50"),
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REF_CLK_GATE(gbe1_125, "gbe_125"),
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REF_CLK_GATE(gbe0_125, "gbe_125"),
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REF_CLK_GATE_DIV(gbe1_core, "gbe_core"),
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REF_CLK_GATE_DIV(gbe0_core, "gbe_core"),
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REF_CLK_GATE_DIV(gbe_bm, "gbe_core"),
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REF_CLK_FULL_DD(sdio),
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REF_CLK_FULL_DD(usb32_usb2_sys),
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REF_CLK_FULL_DD(usb32_ss_sys),
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{ },
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};
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static unsigned int get_div(void __iomem *reg, int shift)
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{
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u32 val;
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val = (readl(reg) >> shift) & 0x7;
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if (val > 6)
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return 0;
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return val;
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}
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static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_double_div *double_div = to_clk_double_div(hw);
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unsigned int div;
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div = get_div(double_div->reg1, double_div->shift1);
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div *= get_div(double_div->reg2, double_div->shift2);
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return DIV_ROUND_UP_ULL((u64)parent_rate, div);
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}
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static const struct clk_ops clk_double_div_ops = {
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.recalc_rate = clk_double_div_recalc_rate,
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};
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static const struct of_device_id armada_3700_periph_clock_of_match[] = {
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{ .compatible = "marvell,armada-3700-periph-clock-nb",
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.data = data_nb, },
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{ .compatible = "marvell,armada-3700-periph-clock-sb",
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.data = data_sb, },
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{ }
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};
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static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
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void __iomem *reg, spinlock_t *lock,
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struct device *dev, struct clk_hw **hw)
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{
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const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
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*rate_ops = NULL;
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struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL;
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if (data->mux_hw) {
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struct clk_mux *mux;
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mux_hw = data->mux_hw;
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mux = to_clk_mux(mux_hw);
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mux->lock = lock;
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mux_ops = mux_hw->init->ops;
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mux->reg = reg + (u64)mux->reg;
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}
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if (data->gate_hw) {
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struct clk_gate *gate;
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gate_hw = data->gate_hw;
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gate = to_clk_gate(gate_hw);
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gate->lock = lock;
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gate_ops = gate_hw->init->ops;
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gate->reg = reg + (u64)gate->reg;
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gate->flags = CLK_GATE_SET_TO_DISABLE;
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}
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if (data->rate_hw) {
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rate_hw = data->rate_hw;
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rate_ops = rate_hw->init->ops;
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if (data->is_double_div) {
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struct clk_double_div *rate;
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rate = to_clk_double_div(rate_hw);
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rate->reg1 = reg + (u64)rate->reg1;
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rate->reg2 = reg + (u64)rate->reg2;
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} else {
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struct clk_divider *rate = to_clk_divider(rate_hw);
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const struct clk_div_table *clkt;
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int table_size = 0;
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rate->reg = reg + (u64)rate->reg;
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for (clkt = rate->table; clkt->div; clkt++)
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table_size++;
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rate->width = order_base_2(table_size);
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rate->lock = lock;
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}
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}
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*hw = clk_hw_register_composite(dev, data->name, data->parent_names,
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data->num_parents, mux_hw,
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mux_ops, rate_hw, rate_ops,
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gate_hw, gate_ops, CLK_IGNORE_UNUSED);
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if (IS_ERR(*hw))
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return PTR_ERR(*hw);
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return 0;
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}
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static int armada_3700_periph_clock_probe(struct platform_device *pdev)
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{
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struct clk_periph_driver_data *driver_data;
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struct device_node *np = pdev->dev.of_node;
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const struct clk_periph_data *data;
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struct device *dev = &pdev->dev;
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int num_periph = 0, i, ret;
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struct resource *res;
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void __iomem *reg;
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data = of_device_get_match_data(dev);
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if (!data)
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return -ENODEV;
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while (data[num_periph].name)
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num_periph++;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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reg = devm_ioremap_resource(dev, res);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
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if (!driver_data)
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return -ENOMEM;
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driver_data->hw_data = devm_kzalloc(dev, sizeof(*driver_data->hw_data) +
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sizeof(*driver_data->hw_data->hws) * num_periph,
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GFP_KERNEL);
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if (!driver_data->hw_data)
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return -ENOMEM;
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driver_data->hw_data->num = num_periph;
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spin_lock_init(&driver_data->lock);
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for (i = 0; i < num_periph; i++) {
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struct clk_hw **hw = &driver_data->hw_data->hws[i];
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if (armada_3700_add_composite_clk(&data[i], reg,
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&driver_data->lock, dev, hw))
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dev_err(dev, "Can't register periph clock %s\n",
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data[i].name);
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}
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
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driver_data->hw_data);
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if (ret) {
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for (i = 0; i < num_periph; i++)
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clk_hw_unregister(driver_data->hw_data->hws[i]);
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return ret;
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}
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platform_set_drvdata(pdev, driver_data);
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return 0;
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}
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static int armada_3700_periph_clock_remove(struct platform_device *pdev)
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{
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struct clk_periph_driver_data *data = platform_get_drvdata(pdev);
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struct clk_hw_onecell_data *hw_data = data->hw_data;
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int i;
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of_clk_del_provider(pdev->dev.of_node);
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for (i = 0; i < hw_data->num; i++)
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clk_hw_unregister(hw_data->hws[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver armada_3700_periph_clock_driver = {
|
|
.probe = armada_3700_periph_clock_probe,
|
|
.remove = armada_3700_periph_clock_remove,
|
|
.driver = {
|
|
.name = "marvell-armada-3700-periph-clock",
|
|
.of_match_table = armada_3700_periph_clock_of_match,
|
|
},
|
|
};
|
|
|
|
builtin_platform_driver(armada_3700_periph_clock_driver);
|