289 lines
6.8 KiB
C
289 lines
6.8 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/ktime.h>
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include "gdsc.h"
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#define PWR_ON_MASK BIT(31)
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#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
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#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
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#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
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#define SW_OVERRIDE_MASK BIT(2)
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#define HW_CONTROL_MASK BIT(1)
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#define SW_COLLAPSE_MASK BIT(0)
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/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
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#define EN_REST_WAIT_VAL (0x2 << 20)
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#define EN_FEW_WAIT_VAL (0x8 << 16)
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#define CLK_DIS_WAIT_VAL (0x2 << 12)
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#define RETAIN_MEM BIT(14)
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#define RETAIN_PERIPH BIT(13)
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#define TIMEOUT_US 100
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#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
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static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
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{
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u32 val;
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int ret;
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ret = regmap_read(sc->regmap, reg, &val);
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if (ret)
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return ret;
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return !!(val & PWR_ON_MASK);
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}
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static int gdsc_toggle_logic(struct gdsc *sc, bool en)
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{
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int ret;
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u32 val = en ? 0 : SW_COLLAPSE_MASK;
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ktime_t start;
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unsigned int status_reg = sc->gdscr;
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ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
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if (ret)
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return ret;
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/* If disabling votable gdscs, don't poll on status */
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if ((sc->flags & VOTABLE) && !en) {
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/*
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* Add a short delay here to ensure that an enable
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* right after it was disabled does not put it in an
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* unknown state
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*/
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udelay(TIMEOUT_US);
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return 0;
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}
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if (sc->gds_hw_ctrl) {
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status_reg = sc->gds_hw_ctrl;
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/*
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* The gds hw controller asserts/de-asserts the status bit soon
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* after it receives a power on/off request from a master.
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* The controller then takes around 8 xo cycles to start its
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* internal state machine and update the status bit. During
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* this time, the status bit does not reflect the true status
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* of the core.
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* Add a delay of 1 us between writing to the SW_COLLAPSE bit
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* and polling the status bit.
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*/
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udelay(1);
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}
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start = ktime_get();
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do {
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if (gdsc_is_enabled(sc, status_reg) == en)
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return 0;
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} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
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if (gdsc_is_enabled(sc, status_reg) == en)
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return 0;
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return -ETIMEDOUT;
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}
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static inline int gdsc_deassert_reset(struct gdsc *sc)
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{
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int i;
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for (i = 0; i < sc->reset_count; i++)
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sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
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return 0;
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}
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static inline int gdsc_assert_reset(struct gdsc *sc)
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{
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int i;
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for (i = 0; i < sc->reset_count; i++)
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sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
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return 0;
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}
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static inline void gdsc_force_mem_on(struct gdsc *sc)
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{
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int i;
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u32 mask = RETAIN_MEM | RETAIN_PERIPH;
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for (i = 0; i < sc->cxc_count; i++)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
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}
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static inline void gdsc_clear_mem_on(struct gdsc *sc)
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{
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int i;
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u32 mask = RETAIN_MEM | RETAIN_PERIPH;
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for (i = 0; i < sc->cxc_count; i++)
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regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
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}
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static int gdsc_enable(struct generic_pm_domain *domain)
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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int ret;
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if (sc->pwrsts == PWRSTS_ON)
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return gdsc_deassert_reset(sc);
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ret = gdsc_toggle_logic(sc, true);
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if (ret)
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return ret;
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if (sc->pwrsts & PWRSTS_OFF)
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gdsc_force_mem_on(sc);
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/*
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* If clocks to this power domain were already on, they will take an
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* additional 4 clock cycles to re-enable after the power domain is
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* enabled. Delay to account for this. A delay is also needed to ensure
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* clocks are not enabled within 400ns of enabling power to the
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* memories.
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*/
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udelay(1);
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return 0;
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}
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static int gdsc_disable(struct generic_pm_domain *domain)
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{
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struct gdsc *sc = domain_to_gdsc(domain);
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if (sc->pwrsts == PWRSTS_ON)
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return gdsc_assert_reset(sc);
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if (sc->pwrsts & PWRSTS_OFF)
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gdsc_clear_mem_on(sc);
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return gdsc_toggle_logic(sc, false);
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}
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static int gdsc_init(struct gdsc *sc)
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{
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u32 mask, val;
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int on, ret;
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unsigned int reg;
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/*
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* Disable HW trigger: collapse/restore occur based on registers writes.
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* Disable SW override: Use hardware state-machine for sequencing.
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* Configure wait time between states.
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*/
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mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
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EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
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val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
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ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
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if (ret)
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return ret;
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/* Force gdsc ON if only ON state is supported */
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if (sc->pwrsts == PWRSTS_ON) {
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ret = gdsc_toggle_logic(sc, true);
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if (ret)
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return ret;
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}
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reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
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on = gdsc_is_enabled(sc, reg);
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if (on < 0)
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return on;
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/*
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* Votable GDSCs can be ON due to Vote from other masters.
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* If a Votable GDSC is ON, make sure we have a Vote.
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*/
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if ((sc->flags & VOTABLE) && on)
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gdsc_enable(&sc->pd);
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if (on || (sc->pwrsts & PWRSTS_RET))
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gdsc_force_mem_on(sc);
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else
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gdsc_clear_mem_on(sc);
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sc->pd.power_off = gdsc_disable;
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sc->pd.power_on = gdsc_enable;
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pm_genpd_init(&sc->pd, NULL, !on);
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return 0;
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}
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int gdsc_register(struct gdsc_desc *desc,
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struct reset_controller_dev *rcdev, struct regmap *regmap)
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{
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int i, ret;
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struct genpd_onecell_data *data;
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struct device *dev = desc->dev;
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struct gdsc **scs = desc->scs;
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size_t num = desc->num;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
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GFP_KERNEL);
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if (!data->domains)
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return -ENOMEM;
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data->num_domains = num;
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for (i = 0; i < num; i++) {
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if (!scs[i])
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continue;
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scs[i]->regmap = regmap;
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scs[i]->rcdev = rcdev;
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ret = gdsc_init(scs[i]);
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if (ret)
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return ret;
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data->domains[i] = &scs[i]->pd;
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}
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/* Add subdomains */
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for (i = 0; i < num; i++) {
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if (!scs[i])
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continue;
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if (scs[i]->parent)
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pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
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}
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return of_genpd_add_provider_onecell(dev->of_node, data);
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}
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void gdsc_unregister(struct gdsc_desc *desc)
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{
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int i;
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struct device *dev = desc->dev;
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struct gdsc **scs = desc->scs;
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size_t num = desc->num;
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/* Remove subdomains */
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for (i = 0; i < num; i++) {
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if (!scs[i])
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continue;
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if (scs[i]->parent)
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pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
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}
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of_genpd_del_provider(dev->of_node);
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}
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