65 lines
3.0 KiB
C
65 lines
3.0 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMD_PCIE_H__
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#define __AMD_PCIE_H__
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/* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
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#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
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/* Following flags shows PCIe link speed supported by ASIC H/W.*/
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
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#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0
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/* gen: chipset 1/2, asic 1/2/3 */
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#define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
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| CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
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| CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
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| CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
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| CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
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/* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
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#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000
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#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000
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#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000
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#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000
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#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000
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#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000
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#define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000
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#define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16
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/* 1/2/4/8/16 lanes */
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#define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
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| CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
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| CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
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| CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
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| CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
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#endif
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