777 lines
25 KiB
C
Executable File
777 lines
25 KiB
C
Executable File
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#ifndef _CGS_COMMON_H
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#define _CGS_COMMON_H
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#include "amd_shared.h"
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struct cgs_device;
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/**
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* enum cgs_gpu_mem_type - GPU memory types
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*/
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enum cgs_gpu_mem_type {
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CGS_GPU_MEM_TYPE__VISIBLE_FB,
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CGS_GPU_MEM_TYPE__INVISIBLE_FB,
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CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
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CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
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CGS_GPU_MEM_TYPE__GART_CACHEABLE,
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CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
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};
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/**
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* enum cgs_ind_reg - Indirect register spaces
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*/
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enum cgs_ind_reg {
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CGS_IND_REG__MMIO,
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CGS_IND_REG__PCIE,
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CGS_IND_REG__SMC,
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CGS_IND_REG__UVD_CTX,
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CGS_IND_REG__DIDT,
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CGS_IND_REG_GC_CAC,
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CGS_IND_REG__AUDIO_ENDPT
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};
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/**
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* enum cgs_clock - Clocks controlled by the SMU
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*/
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enum cgs_clock {
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CGS_CLOCK__SCLK,
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CGS_CLOCK__MCLK,
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CGS_CLOCK__VCLK,
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CGS_CLOCK__DCLK,
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CGS_CLOCK__ECLK,
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CGS_CLOCK__ACLK,
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CGS_CLOCK__ICLK,
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/* ... */
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};
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/**
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* enum cgs_engine - Engines that can be statically power-gated
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*/
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enum cgs_engine {
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CGS_ENGINE__UVD,
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CGS_ENGINE__VCE,
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CGS_ENGINE__VP8,
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CGS_ENGINE__ACP_DMA,
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CGS_ENGINE__ACP_DSP0,
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CGS_ENGINE__ACP_DSP1,
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CGS_ENGINE__ISP,
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/* ... */
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};
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/**
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* enum cgs_voltage_planes - Voltage planes for external camera HW
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*/
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enum cgs_voltage_planes {
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CGS_VOLTAGE_PLANE__SENSOR0,
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CGS_VOLTAGE_PLANE__SENSOR1,
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/* ... */
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};
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/*
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* enum cgs_ucode_id - Firmware types for different IPs
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*/
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enum cgs_ucode_id {
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CGS_UCODE_ID_SMU = 0,
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CGS_UCODE_ID_SMU_SK,
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CGS_UCODE_ID_SDMA0,
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CGS_UCODE_ID_SDMA1,
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CGS_UCODE_ID_CP_CE,
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CGS_UCODE_ID_CP_PFP,
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CGS_UCODE_ID_CP_ME,
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CGS_UCODE_ID_CP_MEC,
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CGS_UCODE_ID_CP_MEC_JT1,
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CGS_UCODE_ID_CP_MEC_JT2,
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CGS_UCODE_ID_GMCON_RENG,
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CGS_UCODE_ID_RLC_G,
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CGS_UCODE_ID_MAXIMUM,
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};
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enum cgs_system_info_id {
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CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1,
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CGS_SYSTEM_INFO_PCIE_GEN_INFO,
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CGS_SYSTEM_INFO_PCIE_MLW,
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CGS_SYSTEM_INFO_PCIE_DEV,
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CGS_SYSTEM_INFO_PCIE_REV,
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CGS_SYSTEM_INFO_CG_FLAGS,
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CGS_SYSTEM_INFO_PG_FLAGS,
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CGS_SYSTEM_INFO_GFX_CU_INFO,
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CGS_SYSTEM_INFO_GFX_SE_INFO,
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CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
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CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
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CGS_SYSTEM_INFO_ID_MAXIMUM,
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};
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struct cgs_system_info {
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uint64_t size;
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enum cgs_system_info_id info_id;
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union {
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void *ptr;
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uint64_t value;
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};
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uint64_t padding[13];
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};
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/*
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* enum cgs_resource_type - GPU resource type
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*/
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enum cgs_resource_type {
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CGS_RESOURCE_TYPE_MMIO = 0,
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CGS_RESOURCE_TYPE_FB,
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CGS_RESOURCE_TYPE_IO,
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CGS_RESOURCE_TYPE_DOORBELL,
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CGS_RESOURCE_TYPE_ROM,
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};
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/**
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* struct cgs_clock_limits - Clock limits
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*
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* Clocks are specified in 10KHz units.
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*/
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struct cgs_clock_limits {
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unsigned min; /**< Minimum supported frequency */
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unsigned max; /**< Maxumim supported frequency */
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unsigned sustainable; /**< Thermally sustainable frequency */
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};
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/**
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* struct cgs_firmware_info - Firmware information
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*/
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struct cgs_firmware_info {
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uint16_t version;
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uint16_t fw_version;
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uint16_t feature_version;
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uint32_t image_size;
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uint64_t mc_addr;
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/* only for smc firmware */
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uint32_t ucode_start_address;
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void *kptr;
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};
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struct cgs_mode_info {
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uint32_t refresh_rate;
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uint32_t ref_clock;
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uint32_t vblank_time_us;
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};
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struct cgs_display_info {
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uint32_t display_count;
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uint32_t active_display_mask;
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struct cgs_mode_info *mode_info;
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};
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typedef unsigned long cgs_handle_t;
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#define CGS_ACPI_METHOD_ATCS 0x53435441
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#define CGS_ACPI_METHOD_ATIF 0x46495441
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#define CGS_ACPI_METHOD_ATPX 0x58505441
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#define CGS_ACPI_FIELD_METHOD_NAME 0x00000001
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#define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002
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#define CGS_ACPI_MAX_BUFFER_SIZE 256
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#define CGS_ACPI_TYPE_ANY 0x00
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#define CGS_ACPI_TYPE_INTEGER 0x01
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#define CGS_ACPI_TYPE_STRING 0x02
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#define CGS_ACPI_TYPE_BUFFER 0x03
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#define CGS_ACPI_TYPE_PACKAGE 0x04
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struct cgs_acpi_method_argument {
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uint32_t type;
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uint32_t data_length;
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union{
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uint32_t value;
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void *pointer;
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};
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};
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struct cgs_acpi_method_info {
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uint32_t size;
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uint32_t field;
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uint32_t input_count;
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uint32_t name;
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struct cgs_acpi_method_argument *pinput_argument;
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uint32_t output_count;
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struct cgs_acpi_method_argument *poutput_argument;
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uint32_t padding[9];
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};
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/**
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* cgs_gpu_mem_info() - Return information about memory heaps
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* @cgs_device: opaque device handle
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* @type: memory type
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* @mc_start: Start MC address of the heap (output)
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* @mc_size: MC address space size (output)
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* @mem_size: maximum amount of memory available for allocation (output)
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*
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* This function returns information about memory heaps. The type
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* parameter is used to select the memory heap. The mc_start and
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* mc_size for GART heaps may be bigger than the memory available for
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* allocation.
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*
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* mc_start and mc_size are undefined for non-contiguous FB memory
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* types, since buffers allocated with these types may or may not be
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* GART mapped.
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
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uint64_t *mc_start, uint64_t *mc_size,
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uint64_t *mem_size);
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/**
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* cgs_gmap_kmem() - map kernel memory to GART aperture
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* @cgs_device: opaque device handle
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* @kmem: pointer to kernel memory
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* @size: size to map
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* @min_offset: minimum offset from start of GART aperture
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* @max_offset: maximum offset from start of GART aperture
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* @kmem_handle: kernel memory handle (output)
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* @mcaddr: MC address (output)
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size,
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uint64_t min_offset, uint64_t max_offset,
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cgs_handle_t *kmem_handle, uint64_t *mcaddr);
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/**
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* cgs_gunmap_kmem() - unmap kernel memory
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* @cgs_device: opaque device handle
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* @kmem_handle: kernel memory handle returned by gmap_kmem
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle);
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/**
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* cgs_alloc_gpu_mem() - Allocate GPU memory
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* @cgs_device: opaque device handle
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* @type: memory type
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* @size: size in bytes
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* @align: alignment in bytes
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* @min_offset: minimum offset from start of heap
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* @max_offset: maximum offset from start of heap
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* @handle: memory handle (output)
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*
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* The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
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* memory allocation. This guarantees that the MC address returned by
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* cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
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* FB memory types may be GART mapped depending on memory
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* fragmentation and memory allocator policies.
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*
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* If min/max_offset are non-0, the allocation will be forced to
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* reside between these offsets in its respective memory heap. The
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* base address that the offset relates to, depends on the memory
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* type.
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*
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* - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
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* - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
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* - others: undefined, don't use with max_offset
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type,
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uint64_t size, uint64_t align,
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uint64_t min_offset, uint64_t max_offset,
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cgs_handle_t *handle);
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/**
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* cgs_free_gpu_mem() - Free GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_gmap_gpu_mem() - GPU-map GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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* @mcaddr: MC address (output)
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*
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* Ensures that a buffer is GPU accessible and returns its MC address.
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
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uint64_t *mcaddr);
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/**
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* cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Allows the buffer to be migrated while it's not used by the GPU.
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_kmap_gpu_mem() - Kernel-map GPU memory
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*
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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* @map: Kernel virtual address the memory was mapped to (output)
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle,
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void **map);
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/**
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* cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
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* @cgs_device: opaque device handle
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* @handle: memory handle returned by alloc or import
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle);
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/**
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* cgs_read_register() - Read an MMIO register
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* @cgs_device: opaque device handle
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* @offset: register offset
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*
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* Return: register value
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*/
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typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset);
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/**
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* cgs_write_register() - Write an MMIO register
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* @cgs_device: opaque device handle
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* @offset: register offset
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* @value: register value
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*/
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typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset,
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uint32_t value);
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/**
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* cgs_read_ind_register() - Read an indirect register
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* @cgs_device: opaque device handle
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* @offset: register offset
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*
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* Return: register value
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*/
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typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
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unsigned index);
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/**
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* cgs_write_ind_register() - Write an indirect register
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* @cgs_device: opaque device handle
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* @offset: register offset
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* @value: register value
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*/
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typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space,
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unsigned index, uint32_t value);
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/**
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* cgs_read_pci_config_byte() - Read byte from PCI configuration space
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* @cgs_device: opaque device handle
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* @addr: address
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*
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* Return: Value read
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*/
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typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr);
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/**
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* cgs_read_pci_config_word() - Read word from PCI configuration space
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* @cgs_device: opaque device handle
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* @addr: address, must be word-aligned
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*
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* Return: Value read
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*/
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typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr);
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/**
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* cgs_read_pci_config_dword() - Read dword from PCI configuration space
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* @cgs_device: opaque device handle
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* @addr: address, must be dword-aligned
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*
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* Return: Value read
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*/
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typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device,
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unsigned addr);
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/**
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* cgs_write_pci_config_byte() - Write byte to PCI configuration space
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* @cgs_device: opaque device handle
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* @addr: address
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* @value: value to write
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*/
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typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr,
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uint8_t value);
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/**
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* cgs_write_pci_config_word() - Write byte to PCI configuration space
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* @cgs_device: opaque device handle
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* @addr: address, must be word-aligned
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* @value: value to write
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*/
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typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr,
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uint16_t value);
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/**
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* cgs_write_pci_config_dword() - Write byte to PCI configuration space
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* @cgs_device: opaque device handle
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* @addr: address, must be dword-aligned
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* @value: value to write
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*/
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typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr,
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uint32_t value);
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/**
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* cgs_get_pci_resource() - provide access to a device resource (PCI BAR)
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* @cgs_device: opaque device handle
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* @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL)
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* @size: size of the region
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* @offset: offset from the start of the region
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* @resource_base: base address (not including offset) returned
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device,
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enum cgs_resource_type resource_type,
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uint64_t size,
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uint64_t offset,
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uint64_t *resource_base);
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/**
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* cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
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* @cgs_device: opaque device handle
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* @table: data table index
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* @size: size of the table (output, may be NULL)
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* @frev: table format revision (output, may be NULL)
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* @crev: table content revision (output, may be NULL)
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*
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* Return: Pointer to start of the table, or NULL on failure
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*/
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typedef const void *(*cgs_atom_get_data_table_t)(
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struct cgs_device *cgs_device, unsigned table,
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uint16_t *size, uint8_t *frev, uint8_t *crev);
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/**
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* cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
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* @cgs_device: opaque device handle
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* @table: data table index
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* @frev: table format revision (output, may be NULL)
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* @crev: table content revision (output, may be NULL)
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*
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* Return: 0 on success, -errno otherwise
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*/
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typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table,
|
|
uint8_t *frev, uint8_t *crev);
|
|
|
|
/**
|
|
* cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
|
|
* @cgs_device: opaque device handle
|
|
* @table: command table index
|
|
* @args: arguments
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device,
|
|
unsigned table, void *args);
|
|
|
|
/**
|
|
* cgs_create_pm_request() - Create a power management request
|
|
* @cgs_device: opaque device handle
|
|
* @request: handle of created PM request (output)
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request);
|
|
|
|
/**
|
|
* cgs_destroy_pm_request() - Destroy a power management request
|
|
* @cgs_device: opaque device handle
|
|
* @request: handle of created PM request
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request);
|
|
|
|
/**
|
|
* cgs_set_pm_request() - Activate or deactiveate a PM request
|
|
* @cgs_device: opaque device handle
|
|
* @request: PM request handle
|
|
* @active: 0 = deactivate, non-0 = activate
|
|
*
|
|
* While a PM request is active, its minimum clock requests are taken
|
|
* into account as the requested engines are powered up. When the
|
|
* request is inactive, the engines may be powered down and clocks may
|
|
* be lower, depending on other PM requests by other driver
|
|
* components.
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request,
|
|
int active);
|
|
|
|
/**
|
|
* cgs_pm_request_clock() - Request a minimum frequency for a specific clock
|
|
* @cgs_device: opaque device handle
|
|
* @request: PM request handle
|
|
* @clock: which clock?
|
|
* @freq: requested min. frequency in 10KHz units (0 to clear request)
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request,
|
|
enum cgs_clock clock, unsigned freq);
|
|
|
|
/**
|
|
* cgs_pm_request_engine() - Request an engine to be powered up
|
|
* @cgs_device: opaque device handle
|
|
* @request: PM request handle
|
|
* @engine: which engine?
|
|
* @powered: 0 = powered down, non-0 = powered up
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request,
|
|
enum cgs_engine engine, int powered);
|
|
|
|
/**
|
|
* cgs_pm_query_clock_limits() - Query clock frequency limits
|
|
* @cgs_device: opaque device handle
|
|
* @clock: which clock?
|
|
* @limits: clock limits
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device,
|
|
enum cgs_clock clock,
|
|
struct cgs_clock_limits *limits);
|
|
|
|
/**
|
|
* cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
|
|
* @cgs_device: opaque device handle
|
|
* @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
|
|
* @voltages: pointer to array of voltage values in 1mV units
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask,
|
|
const uint32_t *voltages);
|
|
/**
|
|
* cgs_get_firmware_info - Get the firmware information from core driver
|
|
* @cgs_device: opaque device handle
|
|
* @type: the firmware type
|
|
* @info: returend firmware information
|
|
*
|
|
* Return: 0 on success, -errno otherwise
|
|
*/
|
|
typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device,
|
|
enum cgs_ucode_id type,
|
|
struct cgs_firmware_info *info);
|
|
|
|
typedef int (*cgs_rel_firmware)(struct cgs_device *cgs_device,
|
|
enum cgs_ucode_id type);
|
|
|
|
typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device,
|
|
enum amd_ip_block_type block_type,
|
|
enum amd_powergating_state state);
|
|
|
|
typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device,
|
|
enum amd_ip_block_type block_type,
|
|
enum amd_clockgating_state state);
|
|
|
|
typedef int(*cgs_get_active_displays_info)(
|
|
struct cgs_device *cgs_device,
|
|
struct cgs_display_info *info);
|
|
|
|
typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled);
|
|
|
|
typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device,
|
|
uint32_t acpi_method,
|
|
uint32_t acpi_function,
|
|
void *pinput, void *poutput,
|
|
uint32_t output_count,
|
|
uint32_t input_size,
|
|
uint32_t output_size);
|
|
|
|
typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device,
|
|
struct cgs_system_info *sys_info);
|
|
|
|
struct cgs_ops {
|
|
/* memory management calls (similar to KFD interface) */
|
|
cgs_gpu_mem_info_t gpu_mem_info;
|
|
cgs_gmap_kmem_t gmap_kmem;
|
|
cgs_gunmap_kmem_t gunmap_kmem;
|
|
cgs_alloc_gpu_mem_t alloc_gpu_mem;
|
|
cgs_free_gpu_mem_t free_gpu_mem;
|
|
cgs_gmap_gpu_mem_t gmap_gpu_mem;
|
|
cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
|
|
cgs_kmap_gpu_mem_t kmap_gpu_mem;
|
|
cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
|
|
/* MMIO access */
|
|
cgs_read_register_t read_register;
|
|
cgs_write_register_t write_register;
|
|
cgs_read_ind_register_t read_ind_register;
|
|
cgs_write_ind_register_t write_ind_register;
|
|
/* PCI configuration space access */
|
|
cgs_read_pci_config_byte_t read_pci_config_byte;
|
|
cgs_read_pci_config_word_t read_pci_config_word;
|
|
cgs_read_pci_config_dword_t read_pci_config_dword;
|
|
cgs_write_pci_config_byte_t write_pci_config_byte;
|
|
cgs_write_pci_config_word_t write_pci_config_word;
|
|
cgs_write_pci_config_dword_t write_pci_config_dword;
|
|
/* PCI resources */
|
|
cgs_get_pci_resource_t get_pci_resource;
|
|
/* ATOM BIOS */
|
|
cgs_atom_get_data_table_t atom_get_data_table;
|
|
cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
|
|
cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
|
|
/* Power management */
|
|
cgs_create_pm_request_t create_pm_request;
|
|
cgs_destroy_pm_request_t destroy_pm_request;
|
|
cgs_set_pm_request_t set_pm_request;
|
|
cgs_pm_request_clock_t pm_request_clock;
|
|
cgs_pm_request_engine_t pm_request_engine;
|
|
cgs_pm_query_clock_limits_t pm_query_clock_limits;
|
|
cgs_set_camera_voltages_t set_camera_voltages;
|
|
/* Firmware Info */
|
|
cgs_get_firmware_info get_firmware_info;
|
|
cgs_rel_firmware rel_firmware;
|
|
/* cg pg interface*/
|
|
cgs_set_powergating_state set_powergating_state;
|
|
cgs_set_clockgating_state set_clockgating_state;
|
|
/* display manager */
|
|
cgs_get_active_displays_info get_active_displays_info;
|
|
/* notify dpm enabled */
|
|
cgs_notify_dpm_enabled notify_dpm_enabled;
|
|
/* ACPI */
|
|
cgs_call_acpi_method call_acpi_method;
|
|
/* get system info */
|
|
cgs_query_system_info query_system_info;
|
|
};
|
|
|
|
struct cgs_os_ops; /* To be define in OS-specific CGS header */
|
|
|
|
struct cgs_device
|
|
{
|
|
const struct cgs_ops *ops;
|
|
const struct cgs_os_ops *os_ops;
|
|
/* to be embedded at the start of driver private structure */
|
|
};
|
|
|
|
/* Convenience macros that make CGS indirect function calls look like
|
|
* normal function calls */
|
|
#define CGS_CALL(func,dev,...) \
|
|
(((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
|
|
#define CGS_OS_CALL(func,dev,...) \
|
|
(((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
|
|
|
|
#define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \
|
|
CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
|
|
#define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
|
|
CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
|
|
#define cgs_gunmap_kmem(dev,kmem_handle) \
|
|
CGS_CALL(gunmap_kmem,dev,keme_handle)
|
|
#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
|
|
CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
|
|
#define cgs_free_gpu_mem(dev,handle) \
|
|
CGS_CALL(free_gpu_mem,dev,handle)
|
|
#define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
|
|
CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
|
|
#define cgs_gunmap_gpu_mem(dev,handle) \
|
|
CGS_CALL(gunmap_gpu_mem,dev,handle)
|
|
#define cgs_kmap_gpu_mem(dev,handle,map) \
|
|
CGS_CALL(kmap_gpu_mem,dev,handle,map)
|
|
#define cgs_kunmap_gpu_mem(dev,handle) \
|
|
CGS_CALL(kunmap_gpu_mem,dev,handle)
|
|
|
|
#define cgs_read_register(dev,offset) \
|
|
CGS_CALL(read_register,dev,offset)
|
|
#define cgs_write_register(dev,offset,value) \
|
|
CGS_CALL(write_register,dev,offset,value)
|
|
#define cgs_read_ind_register(dev,space,index) \
|
|
CGS_CALL(read_ind_register,dev,space,index)
|
|
#define cgs_write_ind_register(dev,space,index,value) \
|
|
CGS_CALL(write_ind_register,dev,space,index,value)
|
|
|
|
#define cgs_read_pci_config_byte(dev,addr) \
|
|
CGS_CALL(read_pci_config_byte,dev,addr)
|
|
#define cgs_read_pci_config_word(dev,addr) \
|
|
CGS_CALL(read_pci_config_word,dev,addr)
|
|
#define cgs_read_pci_config_dword(dev,addr) \
|
|
CGS_CALL(read_pci_config_dword,dev,addr)
|
|
#define cgs_write_pci_config_byte(dev,addr,value) \
|
|
CGS_CALL(write_pci_config_byte,dev,addr,value)
|
|
#define cgs_write_pci_config_word(dev,addr,value) \
|
|
CGS_CALL(write_pci_config_word,dev,addr,value)
|
|
#define cgs_write_pci_config_dword(dev,addr,value) \
|
|
CGS_CALL(write_pci_config_dword,dev,addr,value)
|
|
|
|
#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
|
|
CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
|
|
#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
|
|
CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
|
|
#define cgs_atom_exec_cmd_table(dev,table,args) \
|
|
CGS_CALL(atom_exec_cmd_table,dev,table,args)
|
|
|
|
#define cgs_create_pm_request(dev,request) \
|
|
CGS_CALL(create_pm_request,dev,request)
|
|
#define cgs_destroy_pm_request(dev,request) \
|
|
CGS_CALL(destroy_pm_request,dev,request)
|
|
#define cgs_set_pm_request(dev,request,active) \
|
|
CGS_CALL(set_pm_request,dev,request,active)
|
|
#define cgs_pm_request_clock(dev,request,clock,freq) \
|
|
CGS_CALL(pm_request_clock,dev,request,clock,freq)
|
|
#define cgs_pm_request_engine(dev,request,engine,powered) \
|
|
CGS_CALL(pm_request_engine,dev,request,engine,powered)
|
|
#define cgs_pm_query_clock_limits(dev,clock,limits) \
|
|
CGS_CALL(pm_query_clock_limits,dev,clock,limits)
|
|
#define cgs_set_camera_voltages(dev,mask,voltages) \
|
|
CGS_CALL(set_camera_voltages,dev,mask,voltages)
|
|
#define cgs_get_firmware_info(dev, type, info) \
|
|
CGS_CALL(get_firmware_info, dev, type, info)
|
|
#define cgs_rel_firmware(dev, type) \
|
|
CGS_CALL(rel_firmware, dev, type)
|
|
#define cgs_set_powergating_state(dev, block_type, state) \
|
|
CGS_CALL(set_powergating_state, dev, block_type, state)
|
|
#define cgs_set_clockgating_state(dev, block_type, state) \
|
|
CGS_CALL(set_clockgating_state, dev, block_type, state)
|
|
#define cgs_notify_dpm_enabled(dev, enabled) \
|
|
CGS_CALL(notify_dpm_enabled, dev, enabled)
|
|
|
|
#define cgs_get_active_displays_info(dev, info) \
|
|
CGS_CALL(get_active_displays_info, dev, info)
|
|
|
|
#define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
|
|
CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
|
|
#define cgs_query_system_info(dev, sys_info) \
|
|
CGS_CALL(query_system_info, dev, sys_info)
|
|
#define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \
|
|
resource_base) \
|
|
CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \
|
|
resource_base)
|
|
|
|
#endif /* _CGS_COMMON_H */
|