308 lines
11 KiB
C
308 lines
11 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _SMUMGR_H_
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#define _SMUMGR_H_
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#include <linux/types.h>
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#include "pp_instance.h"
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#include "amd_powerplay.h"
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struct pp_smumgr;
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struct pp_instance;
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struct pp_hwmgr;
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#define smu_lower_32_bits(n) ((uint32_t)(n))
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#define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
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enum AVFS_BTC_STATUS {
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AVFS_BTC_BOOT = 0,
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AVFS_BTC_BOOT_STARTEDSMU,
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AVFS_LOAD_VIRUS,
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AVFS_BTC_VIRUS_LOADED,
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AVFS_BTC_VIRUS_FAIL,
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AVFS_BTC_COMPLETED_PREVIOUSLY,
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AVFS_BTC_ENABLEAVFS,
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AVFS_BTC_STARTED,
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AVFS_BTC_FAILED,
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AVFS_BTC_RESTOREVFT_FAILED,
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AVFS_BTC_SAVEVFT_FAILED,
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AVFS_BTC_DPMTABLESETUP_FAILED,
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AVFS_BTC_COMPLETED_UNSAVED,
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AVFS_BTC_COMPLETED_SAVED,
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AVFS_BTC_COMPLETED_RESTORED,
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AVFS_BTC_DISABLED,
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AVFS_BTC_NOTSUPPORTED,
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AVFS_BTC_SMUMSG_ERROR
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};
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enum SMU_TABLE {
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SMU_UVD_TABLE = 0,
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SMU_VCE_TABLE,
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SMU_SAMU_TABLE,
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SMU_BIF_TABLE,
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};
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enum SMU_TYPE {
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SMU_SoftRegisters = 0,
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SMU_Discrete_DpmTable,
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};
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enum SMU_MEMBER {
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HandshakeDisables = 0,
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VoltageChangeTimeout,
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AverageGraphicsActivity,
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PreVBlankGap,
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VBlankTimeout,
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UcodeLoadStatus,
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UvdBootLevel,
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VceBootLevel,
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SamuBootLevel,
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LowSclkInterruptThreshold,
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};
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enum SMU_MAC_DEFINITION {
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SMU_MAX_LEVELS_GRAPHICS = 0,
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SMU_MAX_LEVELS_MEMORY,
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SMU_MAX_LEVELS_LINK,
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SMU_MAX_ENTRIES_SMIO,
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SMU_MAX_LEVELS_VDDC,
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SMU_MAX_LEVELS_VDDGFX,
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SMU_MAX_LEVELS_VDDCI,
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SMU_MAX_LEVELS_MVDD,
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SMU_UVD_MCLK_HANDSHAKE_DISABLE,
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};
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struct pp_smumgr_func {
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int (*smu_init)(struct pp_smumgr *smumgr);
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int (*smu_fini)(struct pp_smumgr *smumgr);
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int (*start_smu)(struct pp_smumgr *smumgr);
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int (*check_fw_load_finish)(struct pp_smumgr *smumgr,
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uint32_t firmware);
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int (*request_smu_load_fw)(struct pp_smumgr *smumgr);
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int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr,
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uint32_t firmware);
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int (*get_argument)(struct pp_smumgr *smumgr);
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int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg);
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int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr,
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uint16_t msg, uint32_t parameter);
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int (*download_pptable_settings)(struct pp_smumgr *smumgr,
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void **table);
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int (*upload_pptable_settings)(struct pp_smumgr *smumgr);
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int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
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int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
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int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
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int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
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int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
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int (*init_smc_table)(struct pp_hwmgr *hwmgr);
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int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
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int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
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int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
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uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
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uint32_t (*get_mac_definition)(uint32_t value);
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bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
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};
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struct pp_smumgr {
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uint32_t chip_family;
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uint32_t chip_id;
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void *device;
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void *backend;
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uint32_t usec_timeout;
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bool reload_fw;
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const struct pp_smumgr_func *smumgr_funcs;
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};
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extern int smum_init(struct amd_pp_init *pp_init,
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struct pp_instance *handle);
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extern int smum_fini(struct pp_smumgr *smumgr);
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extern int smum_get_argument(struct pp_smumgr *smumgr);
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extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table);
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extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr);
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extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
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extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
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uint16_t msg, uint32_t parameter);
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extern int smum_wait_on_register(struct pp_smumgr *smumgr,
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uint32_t index, uint32_t value, uint32_t mask);
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extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
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uint32_t index, uint32_t value, uint32_t mask);
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extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
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uint32_t indirect_port, uint32_t index,
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uint32_t value, uint32_t mask);
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extern void smum_wait_for_indirect_register_unequal(
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struct pp_smumgr *smumgr,
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uint32_t indirect_port, uint32_t index,
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uint32_t value, uint32_t mask);
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extern int smu_allocate_memory(void *device, uint32_t size,
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enum cgs_gpu_mem_type type,
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uint32_t byte_align, uint64_t *mc_addr,
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void **kptr, void *handle);
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extern int smu_free_memory(void *device, void *handle);
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extern int cz_smum_init(struct pp_smumgr *smumgr);
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extern int iceland_smum_init(struct pp_smumgr *smumgr);
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extern int tonga_smum_init(struct pp_smumgr *smumgr);
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extern int fiji_smum_init(struct pp_smumgr *smumgr);
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extern int polaris10_smum_init(struct pp_smumgr *smumgr);
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extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
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extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
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extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
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extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
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void *input, void *output, void *storage, int result);
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extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
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void *input, void *output, void *storage, int result);
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extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
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extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
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extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
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extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
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extern uint32_t smum_get_offsetof(struct pp_smumgr *smumgr,
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uint32_t type, uint32_t member);
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extern uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value);
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extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
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#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
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#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
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#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
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port, index, value, mask) \
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smum_wait_on_indirect_register(smumgr, \
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mm##port##_INDEX, index, value, mask)
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#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
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SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
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#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
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SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
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SMUM_FIELD_MASK(reg, field) )
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#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
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index, value, mask) \
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smum_wait_for_register_unequal(smumgr, \
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index, value, mask)
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#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \
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SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
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mm##reg, value, mask)
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#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \
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SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \
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(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
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SMUM_FIELD_MASK(reg, field))
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#define SMUM_GET_FIELD(value, reg, field) \
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(((value) & SMUM_FIELD_MASK(reg, field)) \
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>> SMUM_FIELD_SHIFT(reg, field))
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#define SMUM_READ_FIELD(device, reg, field) \
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SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
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#define SMUM_SET_FIELD(value, reg, field, field_val) \
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(((value) & ~SMUM_FIELD_MASK(reg, field)) | \
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(SMUM_FIELD_MASK(reg, field) & ((field_val) << \
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SMUM_FIELD_SHIFT(reg, field))))
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#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
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SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
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reg, field)
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#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
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port, index, value, mask) \
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smum_wait_on_indirect_register(smumgr, \
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mm##port##_INDEX_0, index, value, mask)
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#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
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port, index, value, mask) \
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smum_wait_for_indirect_register_unequal(smumgr, \
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mm##port##_INDEX_0, index, value, mask)
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#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
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SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
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#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
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SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
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/*Operations on named fields.*/
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#define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
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SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
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reg, field)
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#define SMUM_WRITE_FIELD(device, reg, field, fieldval) \
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cgs_write_register(device, mm##reg, \
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SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval))
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#define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
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cgs_write_ind_register(device, port, ix##reg, \
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SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
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reg, field, fieldval))
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#define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
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cgs_write_ind_register(device, port, ix##reg, \
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SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
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reg, field, fieldval))
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#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
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SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \
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(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
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SMUM_FIELD_MASK(reg, field))
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#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
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SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \
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(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
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SMUM_FIELD_MASK(reg, field))
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#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \
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smum_wait_for_indirect_register_unequal(smumgr, \
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mm##port##_INDEX, index, value, mask)
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#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
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SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
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#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
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SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
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SMUM_FIELD_MASK(reg, field) )
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#endif
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