400 lines
14 KiB
C
400 lines
14 KiB
C
/*
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* Copyright (C) 2014 Free Electrons
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* Copyright (C) 2014 Atmel
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef DRM_ATMEL_HLCDC_LAYER_H
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#define DRM_ATMEL_HLCDC_LAYER_H
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#include <linux/mfd/atmel-hlcdc.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_flip_work.h>
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#include <drm/drmP.h>
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#define ATMEL_HLCDC_LAYER_CHER 0x0
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#define ATMEL_HLCDC_LAYER_CHDR 0x4
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#define ATMEL_HLCDC_LAYER_CHSR 0x8
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#define ATMEL_HLCDC_LAYER_DMA_CHAN BIT(0)
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#define ATMEL_HLCDC_LAYER_UPDATE BIT(1)
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#define ATMEL_HLCDC_LAYER_A2Q BIT(2)
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#define ATMEL_HLCDC_LAYER_RST BIT(8)
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#define ATMEL_HLCDC_LAYER_IER 0xc
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#define ATMEL_HLCDC_LAYER_IDR 0x10
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#define ATMEL_HLCDC_LAYER_IMR 0x14
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#define ATMEL_HLCDC_LAYER_ISR 0x18
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#define ATMEL_HLCDC_LAYER_DFETCH BIT(0)
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#define ATMEL_HLCDC_LAYER_LFETCH BIT(1)
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#define ATMEL_HLCDC_LAYER_DMA_IRQ BIT(2)
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#define ATMEL_HLCDC_LAYER_DSCR_IRQ BIT(3)
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#define ATMEL_HLCDC_LAYER_ADD_IRQ BIT(4)
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#define ATMEL_HLCDC_LAYER_DONE_IRQ BIT(5)
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#define ATMEL_HLCDC_LAYER_OVR_IRQ BIT(6)
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#define ATMEL_HLCDC_LAYER_PLANE_HEAD(n) (((n) * 0x10) + 0x1c)
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#define ATMEL_HLCDC_LAYER_PLANE_ADDR(n) (((n) * 0x10) + 0x20)
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#define ATMEL_HLCDC_LAYER_PLANE_CTRL(n) (((n) * 0x10) + 0x24)
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#define ATMEL_HLCDC_LAYER_PLANE_NEXT(n) (((n) * 0x10) + 0x28)
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#define ATMEL_HLCDC_LAYER_CFG(p, c) (((c) * 4) + ((p)->max_planes * 0x10) + 0x1c)
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#define ATMEL_HLCDC_LAYER_DMA_CFG_ID 0
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#define ATMEL_HLCDC_LAYER_DMA_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, ATMEL_HLCDC_LAYER_DMA_CFG_ID)
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#define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4)
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#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4)
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#define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8)
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#define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12)
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#define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13)
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#define ATMEL_HLCDC_LAYER_FORMAT_CFG_ID 1
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#define ATMEL_HLCDC_LAYER_FORMAT_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, ATMEL_HLCDC_LAYER_FORMAT_CFG_ID)
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#define ATMEL_HLCDC_LAYER_RGB (0 << 0)
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#define ATMEL_HLCDC_LAYER_CLUT (1 << 0)
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#define ATMEL_HLCDC_LAYER_YUV (2 << 0)
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#define ATMEL_HLCDC_RGB_MODE(m) (((m) & 0xf) << 4)
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#define ATMEL_HLCDC_CLUT_MODE(m) (((m) & 0x3) << 8)
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#define ATMEL_HLCDC_YUV_MODE(m) (((m) & 0xf) << 12)
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#define ATMEL_HLCDC_YUV422ROT BIT(16)
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#define ATMEL_HLCDC_YUV422SWP BIT(17)
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#define ATMEL_HLCDC_DSCALEOPT BIT(20)
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#define ATMEL_HLCDC_XRGB4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(0))
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#define ATMEL_HLCDC_ARGB4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(1))
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#define ATMEL_HLCDC_RGBA4444_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(2))
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#define ATMEL_HLCDC_RGB565_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(3))
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#define ATMEL_HLCDC_ARGB1555_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(4))
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#define ATMEL_HLCDC_XRGB8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(9))
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#define ATMEL_HLCDC_RGB888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(10))
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#define ATMEL_HLCDC_ARGB8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(12))
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#define ATMEL_HLCDC_RGBA8888_MODE (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(13))
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#define ATMEL_HLCDC_AYUV_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(0))
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#define ATMEL_HLCDC_YUYV_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(1))
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#define ATMEL_HLCDC_UYVY_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(2))
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#define ATMEL_HLCDC_YVYU_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(3))
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#define ATMEL_HLCDC_VYUY_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(4))
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#define ATMEL_HLCDC_NV61_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(5))
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#define ATMEL_HLCDC_YUV422_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(6))
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#define ATMEL_HLCDC_NV21_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(7))
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#define ATMEL_HLCDC_YUV420_MODE (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(8))
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#define ATMEL_HLCDC_LAYER_POS_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.pos)
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#define ATMEL_HLCDC_LAYER_SIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.size)
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#define ATMEL_HLCDC_LAYER_MEMSIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.memsize)
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#define ATMEL_HLCDC_LAYER_XSTRIDE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.xstride)
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#define ATMEL_HLCDC_LAYER_PSTRIDE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.pstride)
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#define ATMEL_HLCDC_LAYER_DFLTCOLOR_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.default_color)
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#define ATMEL_HLCDC_LAYER_CRKEY_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.chroma_key)
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#define ATMEL_HLCDC_LAYER_CRKEY_MASK_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.chroma_key_mask)
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#define ATMEL_HLCDC_LAYER_GENERAL_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.general_config)
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#define ATMEL_HLCDC_LAYER_CRKEY BIT(0)
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#define ATMEL_HLCDC_LAYER_INV BIT(1)
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#define ATMEL_HLCDC_LAYER_ITER2BL BIT(2)
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#define ATMEL_HLCDC_LAYER_ITER BIT(3)
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#define ATMEL_HLCDC_LAYER_REVALPHA BIT(4)
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#define ATMEL_HLCDC_LAYER_GAEN BIT(5)
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#define ATMEL_HLCDC_LAYER_LAEN BIT(6)
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#define ATMEL_HLCDC_LAYER_OVR BIT(7)
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#define ATMEL_HLCDC_LAYER_DMA BIT(8)
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#define ATMEL_HLCDC_LAYER_REP BIT(9)
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#define ATMEL_HLCDC_LAYER_DSTKEY BIT(10)
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#define ATMEL_HLCDC_LAYER_DISCEN BIT(11)
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#define ATMEL_HLCDC_LAYER_GA_SHIFT 16
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#define ATMEL_HLCDC_LAYER_GA_MASK GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
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#define ATMEL_HLCDC_LAYER_GA(x) ((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)
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#define ATMEL_HLCDC_LAYER_CSC_CFG(p, o) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.csc + o)
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#define ATMEL_HLCDC_LAYER_DISC_POS_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.disc_pos)
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#define ATMEL_HLCDC_LAYER_DISC_SIZE_CFG(p) ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.disc_size)
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#define ATMEL_HLCDC_MAX_PLANES 3
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#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0)
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#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1)
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#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2)
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#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3)
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/**
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* Atmel HLCDC Layer registers layout structure
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*
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* Each HLCDC layer has its own register organization and a given register
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* can be placed differently on 2 different layers depending on its
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* capabilities.
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* This structure stores common registers layout for a given layer and is
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* used by HLCDC layer code to choose the appropriate register to write to
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* or to read from.
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*
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* For all fields, a value of zero means "unsupported".
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*
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* See Atmel's datasheet for a detailled description of these registers.
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*
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* @xstride: xstride registers
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* @pstride: pstride registers
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* @pos: position register
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* @size: displayed size register
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* @memsize: memory size register
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* @default_color: default color register
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* @chroma_key: chroma key register
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* @chroma_key_mask: chroma key mask register
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* @general_config: general layer config register
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* @disc_pos: discard area position register
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* @disc_size: discard area size register
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* @csc: color space conversion register
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*/
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struct atmel_hlcdc_layer_cfg_layout {
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int xstride[ATMEL_HLCDC_MAX_PLANES];
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int pstride[ATMEL_HLCDC_MAX_PLANES];
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int pos;
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int size;
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int memsize;
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int default_color;
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int chroma_key;
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int chroma_key_mask;
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int general_config;
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int disc_pos;
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int disc_size;
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int csc;
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};
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/**
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* Atmel HLCDC framebuffer flip structure
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*
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* This structure is allocated when someone asked for a layer update (most
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* likely a DRM plane update, either primary, overlay or cursor plane) and
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* released when the layer do not need to reference the framebuffer object
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* anymore (i.e. the layer was disabled or updated).
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*
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* @dscrs: DMA descriptors
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* @fb: the referenced framebuffer object
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* @ngems: number of GEM objects referenced by the fb element
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* @status: fb flip operation status
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*/
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struct atmel_hlcdc_layer_fb_flip {
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struct atmel_hlcdc_dma_channel_dscr *dscrs[ATMEL_HLCDC_MAX_PLANES];
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struct drm_flip_task *task;
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struct drm_framebuffer *fb;
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int ngems;
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u32 status;
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};
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/**
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* Atmel HLCDC DMA descriptor structure
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*
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* This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
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*
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* The structure fields must remain in this specific order, because they're
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* used by the HLCDC DMA engine, which expect them in this order.
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* HLCDC DMA descriptors must be aligned on 64 bits.
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*
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* @addr: buffer DMA address
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* @ctrl: DMA transfer options
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* @next: next DMA descriptor to fetch
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* @gem_flip: the attached gem_flip operation
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*/
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struct atmel_hlcdc_dma_channel_dscr {
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dma_addr_t addr;
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u32 ctrl;
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dma_addr_t next;
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u32 status;
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} __aligned(sizeof(u64));
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/**
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* Atmel HLCDC layer types
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*/
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enum atmel_hlcdc_layer_type {
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ATMEL_HLCDC_BASE_LAYER,
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ATMEL_HLCDC_OVERLAY_LAYER,
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ATMEL_HLCDC_CURSOR_LAYER,
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ATMEL_HLCDC_PP_LAYER,
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};
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/**
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* Atmel HLCDC Supported formats structure
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*
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* This structure list all the formats supported by a given layer.
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*
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* @nformats: number of supported formats
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* @formats: supported formats
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*/
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struct atmel_hlcdc_formats {
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int nformats;
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uint32_t *formats;
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};
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/**
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* Atmel HLCDC Layer description structure
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*
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* This structure describe the capabilities provided by a given layer.
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*
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* @name: layer name
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* @type: layer type
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* @id: layer id
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* @regs_offset: offset of the layer registers from the HLCDC registers base
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* @nconfigs: number of config registers provided by this layer
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* @formats: supported formats
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* @layout: config registers layout
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* @max_width: maximum width supported by this layer (0 means unlimited)
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* @max_height: maximum height supported by this layer (0 means unlimited)
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*/
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struct atmel_hlcdc_layer_desc {
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const char *name;
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enum atmel_hlcdc_layer_type type;
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int id;
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int regs_offset;
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int nconfigs;
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struct atmel_hlcdc_formats *formats;
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struct atmel_hlcdc_layer_cfg_layout layout;
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int max_width;
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int max_height;
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};
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/**
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* Atmel HLCDC Layer Update Slot structure
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*
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* This structure stores layer update requests to be applied on next frame.
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* This is the base structure behind the atomic layer update infrastructure.
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*
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* Atomic layer update provides a way to update all layer's parameters
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* simultaneously. This is needed to avoid incompatible sequential updates
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* like this one:
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* 1) update layer format from RGB888 (1 plane/buffer) to YUV422
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* (2 planes/buffers)
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* 2) the format update is applied but the DMA channel for the second
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* plane/buffer is not enabled
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* 3) enable the DMA channel for the second plane
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*
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* @fb_flip: fb_flip object
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* @updated_configs: bitmask used to record modified configs
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* @configs: new config values
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*/
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struct atmel_hlcdc_layer_update_slot {
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struct atmel_hlcdc_layer_fb_flip *fb_flip;
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unsigned long *updated_configs;
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u32 *configs;
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};
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/**
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* Atmel HLCDC Layer Update structure
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*
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* This structure provides a way to queue layer update requests.
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*
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* At a given time there is at most:
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* - one pending update request, which means the update request has been
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* committed (or validated) and is waiting for the DMA channel(s) to be
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* available
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* - one request being prepared, which means someone started a layer update
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* but has not committed it yet. There cannot be more than one started
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* request, because the update lock is taken when starting a layer update
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* and release when committing or rolling back the request.
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*
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* @slots: update slots. One is used for pending request and the other one
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* for started update request
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* @pending: the pending slot index or -1 if no request is pending
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* @next: the started update slot index or -1 no update has been started
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*/
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struct atmel_hlcdc_layer_update {
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struct atmel_hlcdc_layer_update_slot slots[2];
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int pending;
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int next;
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};
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enum atmel_hlcdc_layer_dma_channel_status {
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ATMEL_HLCDC_LAYER_DISABLED,
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ATMEL_HLCDC_LAYER_ENABLED,
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ATMEL_HLCDC_LAYER_DISABLING,
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};
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/**
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* Atmel HLCDC Layer DMA channel structure
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*
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* This structure stores information on the DMA channel associated to a
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* given layer.
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*
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* @status: DMA channel status
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* @cur: current framebuffer
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* @queue: next framebuffer
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* @dscrs: allocated DMA descriptors
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*/
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struct atmel_hlcdc_layer_dma_channel {
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enum atmel_hlcdc_layer_dma_channel_status status;
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struct atmel_hlcdc_layer_fb_flip *cur;
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struct atmel_hlcdc_layer_fb_flip *queue;
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struct atmel_hlcdc_dma_channel_dscr *dscrs;
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};
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/**
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* Atmel HLCDC Layer structure
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*
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* This structure stores information on the layer instance.
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*
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* @desc: layer description
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* @max_planes: maximum planes/buffers that can be associated with this layer.
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* This depends on the supported formats.
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* @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
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* @dma: dma channel
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* @gc: fb flip garbage collector
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* @update: update handler
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* @lock: layer lock
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*/
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struct atmel_hlcdc_layer {
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const struct atmel_hlcdc_layer_desc *desc;
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int max_planes;
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struct atmel_hlcdc *hlcdc;
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struct workqueue_struct *wq;
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struct drm_flip_work gc;
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struct atmel_hlcdc_layer_dma_channel dma;
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struct atmel_hlcdc_layer_update update;
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spinlock_t lock;
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};
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void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer);
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int atmel_hlcdc_layer_init(struct drm_device *dev,
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struct atmel_hlcdc_layer *layer,
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const struct atmel_hlcdc_layer_desc *desc);
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void atmel_hlcdc_layer_cleanup(struct drm_device *dev,
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struct atmel_hlcdc_layer *layer);
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void atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer);
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int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer);
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void atmel_hlcdc_layer_update_cfg(struct atmel_hlcdc_layer *layer, int cfg,
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u32 mask, u32 val);
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void atmel_hlcdc_layer_update_set_fb(struct atmel_hlcdc_layer *layer,
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struct drm_framebuffer *fb,
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unsigned int *offsets);
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void atmel_hlcdc_layer_update_set_finished(struct atmel_hlcdc_layer *layer,
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void (*finished)(void *data),
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void *finished_data);
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void atmel_hlcdc_layer_update_rollback(struct atmel_hlcdc_layer *layer);
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void atmel_hlcdc_layer_update_commit(struct atmel_hlcdc_layer *layer);
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#endif /* DRM_ATMEL_HLCDC_LAYER_H */
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