715 lines
22 KiB
C
715 lines
22 KiB
C
/*
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* Copyright © 2008-2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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/**
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* DOC: fence register handling
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*
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* Important to avoid confusions: "fences" in the i915 driver are not execution
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* fences used to track command completion but hardware detiler objects which
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* wrap a given range of the global GTT. Each platform has only a fairly limited
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* set of these objects.
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*
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* Fences are used to detile GTT memory mappings. They're also connected to the
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* hardware frontbuffer render tracking and hence interact with frontbuffer
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* compression. Furthermore on older platforms fences are required for tiled
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* objects used by the display engine. They can also be used by the render
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* engine - they're required for blitter commands and are optional for render
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* commands. But on gen4+ both display (with the exception of fbc) and rendering
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* have their own tiling state bits and don't need fences.
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*
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* Also note that fences only support X and Y tiling and hence can't be used for
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* the fancier new tiling formats like W, Ys and Yf.
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*
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* Finally note that because fences are such a restricted resource they're
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* dynamically associated with objects. Furthermore fence state is committed to
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* the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
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* explicitly call i915_gem_object_get_fence() to synchronize fencing status
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* for cpu access. Also note that some code wants an unfenced view, for those
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* cases the fence can be removed forcefully with i915_gem_object_put_fence().
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*
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* Internally these functions will synchronize with userspace access by removing
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* CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
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*/
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#define pipelined 0
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static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
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struct i915_vma *vma)
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{
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i915_reg_t fence_reg_lo, fence_reg_hi;
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int fence_pitch_shift;
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u64 val;
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if (INTEL_INFO(fence->i915)->gen >= 6) {
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fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
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fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
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fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
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} else {
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fence_reg_lo = FENCE_REG_965_LO(fence->id);
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fence_reg_hi = FENCE_REG_965_HI(fence->id);
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fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
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}
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val = 0;
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if (vma) {
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unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
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bool is_y_tiled = tiling == I915_TILING_Y;
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unsigned int stride = i915_gem_object_get_stride(vma->obj);
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u32 row_size = stride * (is_y_tiled ? 32 : 8);
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u32 size = rounddown((u32)vma->node.size, row_size);
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val = ((vma->node.start + size - 4096) & 0xfffff000) << 32;
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val |= vma->node.start & 0xfffff000;
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val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
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if (is_y_tiled)
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val |= BIT(I965_FENCE_TILING_Y_SHIFT);
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val |= I965_FENCE_REG_VALID;
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}
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if (!pipelined) {
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struct drm_i915_private *dev_priv = fence->i915;
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/* To w/a incoherency with non-atomic 64-bit register updates,
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* we split the 64-bit update into two 32-bit writes. In order
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* for a partial fence not to be evaluated between writes, we
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* precede the update with write to turn off the fence register,
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* and only enable the fence as the last step.
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*
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* For extra levels of paranoia, we make sure each step lands
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* before applying the next step.
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*/
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I915_WRITE(fence_reg_lo, 0);
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POSTING_READ(fence_reg_lo);
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I915_WRITE(fence_reg_hi, upper_32_bits(val));
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I915_WRITE(fence_reg_lo, lower_32_bits(val));
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POSTING_READ(fence_reg_lo);
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}
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}
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static void i915_write_fence_reg(struct drm_i915_fence_reg *fence,
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struct i915_vma *vma)
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{
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u32 val;
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val = 0;
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if (vma) {
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unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
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bool is_y_tiled = tiling == I915_TILING_Y;
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unsigned int stride = i915_gem_object_get_stride(vma->obj);
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int pitch_val;
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int tile_width;
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WARN((vma->node.start & ~I915_FENCE_START_MASK) ||
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!is_power_of_2(vma->node.size) ||
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(vma->node.start & (vma->node.size - 1)),
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"object 0x%08llx [fenceable? %d] not 1M or pot-size (0x%08llx) aligned\n",
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vma->node.start,
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i915_vma_is_map_and_fenceable(vma),
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vma->node.size);
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if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence->i915))
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tile_width = 128;
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else
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tile_width = 512;
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/* Note: pitch better be a power of two tile widths */
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pitch_val = stride / tile_width;
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pitch_val = ffs(pitch_val) - 1;
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val = vma->node.start;
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if (is_y_tiled)
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val |= BIT(I830_FENCE_TILING_Y_SHIFT);
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val |= I915_FENCE_SIZE_BITS(vma->node.size);
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val |= pitch_val << I830_FENCE_PITCH_SHIFT;
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val |= I830_FENCE_REG_VALID;
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}
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if (!pipelined) {
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struct drm_i915_private *dev_priv = fence->i915;
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i915_reg_t reg = FENCE_REG(fence->id);
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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}
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}
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static void i830_write_fence_reg(struct drm_i915_fence_reg *fence,
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struct i915_vma *vma)
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{
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u32 val;
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val = 0;
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if (vma) {
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unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
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bool is_y_tiled = tiling == I915_TILING_Y;
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unsigned int stride = i915_gem_object_get_stride(vma->obj);
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u32 pitch_val;
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WARN((vma->node.start & ~I830_FENCE_START_MASK) ||
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!is_power_of_2(vma->node.size) ||
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(vma->node.start & (vma->node.size - 1)),
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"object 0x%08llx not 512K or pot-size 0x%08llx aligned\n",
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vma->node.start, vma->node.size);
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pitch_val = stride / 128;
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pitch_val = ffs(pitch_val) - 1;
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val = vma->node.start;
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if (is_y_tiled)
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val |= BIT(I830_FENCE_TILING_Y_SHIFT);
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val |= I830_FENCE_SIZE_BITS(vma->node.size);
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val |= pitch_val << I830_FENCE_PITCH_SHIFT;
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val |= I830_FENCE_REG_VALID;
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}
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if (!pipelined) {
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struct drm_i915_private *dev_priv = fence->i915;
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i915_reg_t reg = FENCE_REG(fence->id);
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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}
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}
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static void fence_write(struct drm_i915_fence_reg *fence,
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struct i915_vma *vma)
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{
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/* Previous access through the fence register is marshalled by
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* the mb() inside the fault handlers (i915_gem_release_mmaps)
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* and explicitly managed for internal users.
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*/
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if (IS_GEN2(fence->i915))
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i830_write_fence_reg(fence, vma);
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else if (IS_GEN3(fence->i915))
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i915_write_fence_reg(fence, vma);
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else
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i965_write_fence_reg(fence, vma);
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/* Access through the fenced region afterwards is
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* ordered by the posting reads whilst writing the registers.
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*/
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fence->dirty = false;
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}
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static int fence_update(struct drm_i915_fence_reg *fence,
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struct i915_vma *vma)
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{
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int ret;
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if (vma) {
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if (!i915_vma_is_map_and_fenceable(vma))
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return -EINVAL;
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if (WARN(!i915_gem_object_get_stride(vma->obj) ||
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!i915_gem_object_get_tiling(vma->obj),
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"bogus fence setup with stride: 0x%x, tiling mode: %i\n",
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i915_gem_object_get_stride(vma->obj),
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i915_gem_object_get_tiling(vma->obj)))
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return -EINVAL;
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ret = i915_gem_active_retire(&vma->last_fence,
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&vma->obj->base.dev->struct_mutex);
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if (ret)
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return ret;
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}
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if (fence->vma) {
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ret = i915_gem_active_retire(&fence->vma->last_fence,
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&fence->vma->obj->base.dev->struct_mutex);
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if (ret)
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return ret;
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}
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if (fence->vma && fence->vma != vma) {
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/* Ensure that all userspace CPU access is completed before
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* stealing the fence.
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*/
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i915_gem_release_mmap(fence->vma->obj);
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fence->vma->fence = NULL;
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fence->vma = NULL;
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list_move(&fence->link, &fence->i915->mm.fence_list);
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}
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fence_write(fence, vma);
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if (vma) {
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if (fence->vma != vma) {
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vma->fence = fence;
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fence->vma = vma;
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}
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list_move_tail(&fence->link, &fence->i915->mm.fence_list);
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}
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return 0;
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}
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/**
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* i915_vma_put_fence - force-remove fence for a VMA
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* @vma: vma to map linearly (not through a fence reg)
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*
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* This function force-removes any fence from the given object, which is useful
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* if the kernel wants to do untiled GTT access.
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*
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* Returns:
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*
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* 0 on success, negative error code on failure.
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*/
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int
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i915_vma_put_fence(struct i915_vma *vma)
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{
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struct drm_i915_fence_reg *fence = vma->fence;
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assert_rpm_wakelock_held(to_i915(vma->vm->dev));
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if (!fence)
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return 0;
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if (fence->pin_count)
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return -EBUSY;
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return fence_update(fence, NULL);
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}
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static struct drm_i915_fence_reg *fence_find(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_fence_reg *fence;
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list_for_each_entry(fence, &dev_priv->mm.fence_list, link) {
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if (fence->pin_count)
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continue;
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return fence;
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}
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/* Wait for completion of pending flips which consume fences */
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if (intel_has_pending_fb_unpin(&dev_priv->drm))
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return ERR_PTR(-EAGAIN);
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return ERR_PTR(-EDEADLK);
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}
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/**
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* i915_vma_get_fence - set up fencing for a vma
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* @vma: vma to map through a fence reg
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*
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* When mapping objects through the GTT, userspace wants to be able to write
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* to them without having to worry about swizzling if the object is tiled.
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* This function walks the fence regs looking for a free one for @obj,
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* stealing one if it can't find any.
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*
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* It then sets up the reg based on the object's properties: address, pitch
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* and tiling format.
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*
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* For an untiled surface, this removes any existing fence.
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*
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* Returns:
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*
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* 0 on success, negative error code on failure.
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*/
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int
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i915_vma_get_fence(struct i915_vma *vma)
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{
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struct drm_i915_fence_reg *fence;
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struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
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assert_rpm_wakelock_held(to_i915(vma->vm->dev));
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/* Just update our place in the LRU if our fence is getting reused. */
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if (vma->fence) {
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fence = vma->fence;
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if (!fence->dirty) {
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list_move_tail(&fence->link,
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&fence->i915->mm.fence_list);
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return 0;
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}
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} else if (set) {
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fence = fence_find(to_i915(vma->vm->dev));
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if (IS_ERR(fence))
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return PTR_ERR(fence);
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} else
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return 0;
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return fence_update(fence, set);
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}
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/**
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* i915_gem_restore_fences - restore fence state
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* @dev: DRM device
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*
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* Restore the hw fence state to match the software tracking again, to be called
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* after a gpu reset and on resume.
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*/
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void i915_gem_restore_fences(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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int i;
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/* Note that this may be called outside of struct_mutex, by
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* runtime suspend/resume. The barrier we require is enforced by
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* rpm itself - all access to fences/GTT are only within an rpm
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* wakeref, and to acquire that wakeref you must pass through here.
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*/
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for (i = 0; i < dev_priv->num_fence_regs; i++) {
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struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
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struct i915_vma *vma = reg->vma;
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/*
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* Commit delayed tiling changes if we have an object still
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* attached to the fence, otherwise just clear the fence.
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*/
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if (vma && !i915_gem_object_is_tiled(vma->obj)) {
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GEM_BUG_ON(!reg->dirty);
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GEM_BUG_ON(vma->obj->fault_mappable);
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list_move(®->link, &dev_priv->mm.fence_list);
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vma->fence = NULL;
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vma = NULL;
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}
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fence_write(reg, vma);
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reg->vma = vma;
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}
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}
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/**
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* DOC: tiling swizzling details
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*
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* The idea behind tiling is to increase cache hit rates by rearranging
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* pixel data so that a group of pixel accesses are in the same cacheline.
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* Performance improvement from doing this on the back/depth buffer are on
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* the order of 30%.
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*
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* Intel architectures make this somewhat more complicated, though, by
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* adjustments made to addressing of data when the memory is in interleaved
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* mode (matched pairs of DIMMS) to improve memory bandwidth.
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* For interleaved memory, the CPU sends every sequential 64 bytes
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* to an alternate memory channel so it can get the bandwidth from both.
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*
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* The GPU also rearranges its accesses for increased bandwidth to interleaved
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* memory, and it matches what the CPU does for non-tiled. However, when tiled
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* it does it a little differently, since one walks addresses not just in the
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* X direction but also Y. So, along with alternating channels when bit
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* 6 of the address flips, it also alternates when other bits flip -- Bits 9
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* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
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* are common to both the 915 and 965-class hardware.
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*
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* The CPU also sometimes XORs in higher bits as well, to improve
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* bandwidth doing strided access like we do so frequently in graphics. This
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* is called "Channel XOR Randomization" in the MCH documentation. The result
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* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
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* decode.
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*
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* All of this bit 6 XORing has an effect on our memory management,
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* as we need to make sure that the 3d driver can correctly address object
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* contents.
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*
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* If we don't have interleaved memory, all tiling is safe and no swizzling is
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* required.
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*
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* When bit 17 is XORed in, we simply refuse to tile at all. Bit
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* 17 is not just a page offset, so as we page an object out and back in,
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* individual pages in it will have different bit 17 addresses, resulting in
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* each 64 bytes being swapped with its neighbor!
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*
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* Otherwise, if interleaved, we have to tell the 3d driver what the address
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* swizzling it needs to do is, since it's writing with the CPU to the pages
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* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
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* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
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* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
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* to match what the GPU expects.
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*/
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/**
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* i915_gem_detect_bit_6_swizzle - detect bit 6 swizzling pattern
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* @dev: DRM device
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*
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* Detects bit 6 swizzling of address lookup between IGD access and CPU
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* access through main memory.
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*/
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void
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i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
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/*
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* On BDW+, swizzling is not used. We leave the CPU memory
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* controller in charge of optimizing memory accesses without
|
|
* the extra address manipulation GPU side.
|
|
*
|
|
* VLV and CHV don't have GPU swizzling.
|
|
*/
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
} else if (INTEL_INFO(dev)->gen >= 6) {
|
|
if (dev_priv->preserve_bios_swizzle) {
|
|
if (I915_READ(DISP_ARB_CTL) &
|
|
DISP_TILE_SURFACE_SWIZZLING) {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
} else {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
}
|
|
} else {
|
|
uint32_t dimm_c0, dimm_c1;
|
|
dimm_c0 = I915_READ(MAD_DIMM_C0);
|
|
dimm_c1 = I915_READ(MAD_DIMM_C1);
|
|
dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
|
|
dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
|
|
/* Enable swizzling when the channels are populated
|
|
* with identically sized dimms. We don't need to check
|
|
* the 3rd channel because no cpu with gpu attached
|
|
* ships in that configuration. Also, swizzling only
|
|
* makes sense for 2 channels anyway. */
|
|
if (dimm_c0 == dimm_c1) {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
} else {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
}
|
|
}
|
|
} else if (IS_GEN5(dev)) {
|
|
/* On Ironlake whatever DRAM config, GPU always do
|
|
* same swizzling setup.
|
|
*/
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
} else if (IS_GEN2(dev)) {
|
|
/* As far as we know, the 865 doesn't have these bit 6
|
|
* swizzling issues.
|
|
*/
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
|
|
uint32_t dcc;
|
|
|
|
/* On 9xx chipsets, channel interleave by the CPU is
|
|
* determined by DCC. For single-channel, neither the CPU
|
|
* nor the GPU do swizzling. For dual channel interleaved,
|
|
* the GPU's interleave is bit 9 and 10 for X tiled, and bit
|
|
* 9 for Y tiled. The CPU's interleave is independent, and
|
|
* can be based on either bit 11 (haven't seen this yet) or
|
|
* bit 17 (common).
|
|
*/
|
|
dcc = I915_READ(DCC);
|
|
switch (dcc & DCC_ADDRESSING_MODE_MASK) {
|
|
case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
|
|
case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
break;
|
|
case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
|
|
if (dcc & DCC_CHANNEL_XOR_DISABLE) {
|
|
/* This is the base swizzling by the GPU for
|
|
* tiled buffers.
|
|
*/
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
|
|
/* Bit 11 swizzling by the CPU in addition. */
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9_11;
|
|
} else {
|
|
/* Bit 17 swizzling by the CPU in addition. */
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9_17;
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* check for L-shaped memory aka modified enhanced addressing */
|
|
if (IS_GEN4(dev) &&
|
|
!(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
}
|
|
|
|
if (dcc == 0xffffffff) {
|
|
DRM_ERROR("Couldn't read from MCHBAR. "
|
|
"Disabling tiling.\n");
|
|
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
}
|
|
} else {
|
|
/* The 965, G33, and newer, have a very flexible memory
|
|
* configuration. It will enable dual-channel mode
|
|
* (interleaving) on as much memory as it can, and the GPU
|
|
* will additionally sometimes enable different bit 6
|
|
* swizzling for tiled objects from the CPU.
|
|
*
|
|
* Here's what I found on the G965:
|
|
* slot fill memory size swizzling
|
|
* 0A 0B 1A 1B 1-ch 2-ch
|
|
* 512 0 0 0 512 0 O
|
|
* 512 0 512 0 16 1008 X
|
|
* 512 0 0 512 16 1008 X
|
|
* 0 512 0 512 16 1008 X
|
|
* 1024 1024 1024 0 2048 1024 O
|
|
*
|
|
* We could probably detect this based on either the DRB
|
|
* matching, which was the case for the swizzling required in
|
|
* the table above, or from the 1-ch value being less than
|
|
* the minimum size of a rank.
|
|
*
|
|
* Reports indicate that the swizzling actually
|
|
* varies depending upon page placement inside the
|
|
* channels, i.e. we see swizzled pages where the
|
|
* banks of memory are paired and unswizzled on the
|
|
* uneven portion, so leave that as unknown.
|
|
*/
|
|
if (I915_READ16(C0DRB3) == I915_READ16(C1DRB3)) {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
}
|
|
}
|
|
|
|
if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
|
|
swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
|
|
/* Userspace likes to explode if it sees unknown swizzling,
|
|
* so lie. We will finish the lie when reporting through
|
|
* the get-tiling-ioctl by reporting the physical swizzle
|
|
* mode as unknown instead.
|
|
*
|
|
* As we don't strictly know what the swizzling is, it may be
|
|
* bit17 dependent, and so we need to also prevent the pages
|
|
* from being moved.
|
|
*/
|
|
dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
}
|
|
|
|
dev_priv->mm.bit_6_swizzle_x = swizzle_x;
|
|
dev_priv->mm.bit_6_swizzle_y = swizzle_y;
|
|
}
|
|
|
|
/*
|
|
* Swap every 64 bytes of this page around, to account for it having a new
|
|
* bit 17 of its physical address and therefore being interpreted differently
|
|
* by the GPU.
|
|
*/
|
|
static void
|
|
i915_gem_swizzle_page(struct page *page)
|
|
{
|
|
char temp[64];
|
|
char *vaddr;
|
|
int i;
|
|
|
|
vaddr = kmap(page);
|
|
|
|
for (i = 0; i < PAGE_SIZE; i += 128) {
|
|
memcpy(temp, &vaddr[i], 64);
|
|
memcpy(&vaddr[i], &vaddr[i + 64], 64);
|
|
memcpy(&vaddr[i + 64], temp, 64);
|
|
}
|
|
|
|
kunmap(page);
|
|
}
|
|
|
|
/**
|
|
* i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling
|
|
* @obj: i915 GEM buffer object
|
|
*
|
|
* This function fixes up the swizzling in case any page frame number for this
|
|
* object has changed in bit 17 since that state has been saved with
|
|
* i915_gem_object_save_bit_17_swizzle().
|
|
*
|
|
* This is called when pinning backing storage again, since the kernel is free
|
|
* to move unpinned backing storage around (either by directly moving pages or
|
|
* by swapping them out and back in again).
|
|
*/
|
|
void
|
|
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct sgt_iter sgt_iter;
|
|
struct page *page;
|
|
int i;
|
|
|
|
if (obj->bit_17 == NULL)
|
|
return;
|
|
|
|
i = 0;
|
|
for_each_sgt_page(page, sgt_iter, obj->pages) {
|
|
char new_bit_17 = page_to_phys(page) >> 17;
|
|
if ((new_bit_17 & 0x1) !=
|
|
(test_bit(i, obj->bit_17) != 0)) {
|
|
i915_gem_swizzle_page(page);
|
|
set_page_dirty(page);
|
|
}
|
|
i++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling
|
|
* @obj: i915 GEM buffer object
|
|
*
|
|
* This function saves the bit 17 of each page frame number so that swizzling
|
|
* can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must
|
|
* be called before the backing storage can be unpinned.
|
|
*/
|
|
void
|
|
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct sgt_iter sgt_iter;
|
|
struct page *page;
|
|
int page_count = obj->base.size >> PAGE_SHIFT;
|
|
int i;
|
|
|
|
if (obj->bit_17 == NULL) {
|
|
obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
|
|
sizeof(long), GFP_KERNEL);
|
|
if (obj->bit_17 == NULL) {
|
|
DRM_ERROR("Failed to allocate memory for bit 17 "
|
|
"record\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
i = 0;
|
|
|
|
for_each_sgt_page(page, sgt_iter, obj->pages) {
|
|
if (page_to_phys(page) & (1 << 17))
|
|
__set_bit(i, obj->bit_17);
|
|
else
|
|
__clear_bit(i, obj->bit_17);
|
|
i++;
|
|
}
|
|
}
|