153 lines
9.4 KiB
C
153 lines
9.4 KiB
C
#ifndef __NVIF_CLASS_H__
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#define __NVIF_CLASS_H__
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/* these class numbers are made up by us, and not nvidia-assigned */
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#define NVIF_CLASS_CONTROL /* if0001.h */ -1
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#define NVIF_CLASS_PERFMON /* if0002.h */ -2
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#define NVIF_CLASS_PERFDOM /* if0003.h */ -3
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#define NVIF_CLASS_SW_NV04 /* if0004.h */ -4
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#define NVIF_CLASS_SW_NV10 /* if0005.h */ -5
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#define NVIF_CLASS_SW_NV50 /* if0005.h */ -6
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#define NVIF_CLASS_SW_GF100 /* if0005.h */ -7
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/* the below match nvidia-assigned (either in hw, or sw) class numbers */
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#define NV_DEVICE /* cl0080.h */ 0x00000080
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#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
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#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
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#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
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#define FERMI_TWOD_A 0x0000902d
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#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
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#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
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#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
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#define NV04_DISP /* cl0046.h */ 0x00000046
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#define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
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#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
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#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
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#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
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#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
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#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
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#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
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#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
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#define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f
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#define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f
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#define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f
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#define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
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#define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f
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#define NV50_DISP /* cl5070.h */ 0x00005070
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#define G82_DISP /* cl5070.h */ 0x00008270
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#define GT200_DISP /* cl5070.h */ 0x00008370
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#define GT214_DISP /* cl5070.h */ 0x00008570
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#define GT206_DISP /* cl5070.h */ 0x00008870
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#define GF110_DISP /* cl5070.h */ 0x00009070
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#define GK104_DISP /* cl5070.h */ 0x00009170
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#define GK110_DISP /* cl5070.h */ 0x00009270
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#define GM107_DISP /* cl5070.h */ 0x00009470
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#define GM200_DISP /* cl5070.h */ 0x00009570
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#define GP100_DISP /* cl5070.h */ 0x00009770
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#define GP104_DISP /* cl5070.h */ 0x00009870
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#define NV31_MPEG 0x00003174
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#define G82_MPEG 0x00008274
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#define NV74_VP2 0x00007476
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#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a
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#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a
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#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a
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#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
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#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
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#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
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#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
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#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b
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#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b
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#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
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#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
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#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
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#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c
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#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c
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#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c
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#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c
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#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c
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#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d
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#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d
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#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d
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#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d
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#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d
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#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d
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#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d
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#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d
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#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d
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#define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d
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#define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
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#define GP104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
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#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
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#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
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#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e
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#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e
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#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e
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#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
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#define FERMI_A /* cl9097.h */ 0x00009097
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#define FERMI_B /* cl9097.h */ 0x00009197
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#define FERMI_C /* cl9097.h */ 0x00009297
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#define KEPLER_A /* cl9097.h */ 0x0000a097
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#define KEPLER_B /* cl9097.h */ 0x0000a197
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#define KEPLER_C /* cl9097.h */ 0x0000a297
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#define MAXWELL_A /* cl9097.h */ 0x0000b097
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#define MAXWELL_B /* cl9097.h */ 0x0000b197
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#define PASCAL_A /* cl9097.h */ 0x0000c097
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#define NV74_BSP 0x000074b0
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#define GT212_MSVLD 0x000085b1
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#define IGT21A_MSVLD 0x000086b1
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#define G98_MSVLD 0x000088b1
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#define GF100_MSVLD 0x000090b1
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#define GK104_MSVLD 0x000095b1
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#define GT212_MSPDEC 0x000085b2
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#define G98_MSPDEC 0x000088b2
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#define GF100_MSPDEC 0x000090b2
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#define GK104_MSPDEC 0x000095b2
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#define GT212_MSPPP 0x000085b3
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#define G98_MSPPP 0x000088b3
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#define GF100_MSPPP 0x000090b3
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#define G98_SEC 0x000088b4
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#define GT212_DMA 0x000085b5
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#define FERMI_DMA 0x000090b5
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#define KEPLER_DMA_COPY_A 0x0000a0b5
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#define MAXWELL_DMA_COPY_A 0x0000b0b5
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#define PASCAL_DMA_COPY_A 0x0000c0b5
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#define PASCAL_DMA_COPY_B 0x0000c1b5
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#define FERMI_DECOMPRESS 0x000090b8
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#define FERMI_COMPUTE_A 0x000090c0
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#define FERMI_COMPUTE_B 0x000091c0
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#define KEPLER_COMPUTE_A 0x0000a0c0
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#define KEPLER_COMPUTE_B 0x0000a1c0
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#define MAXWELL_COMPUTE_A 0x0000b0c0
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#define MAXWELL_COMPUTE_B 0x0000b1c0
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#define PASCAL_COMPUTE_A 0x0000c0c0
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#define NV74_CIPHER 0x000074c1
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#endif
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