568 lines
15 KiB
C
568 lines
15 KiB
C
/*
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* Copyright (C) 2015 Red Hat, Inc.
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* All Rights Reserved.
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*
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* Authors:
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* Dave Airlie
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* Alon Levy
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <drm/drmP.h>
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#include "virtgpu_drv.h"
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#include <drm/virtgpu_drm.h>
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#include "ttm/ttm_execbuf_util.h"
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static void convert_to_hw_box(struct virtio_gpu_box *dst,
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const struct drm_virtgpu_3d_box *src)
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{
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dst->x = cpu_to_le32(src->x);
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dst->y = cpu_to_le32(src->y);
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dst->z = cpu_to_le32(src->z);
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dst->w = cpu_to_le32(src->w);
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dst->h = cpu_to_le32(src->h);
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dst->d = cpu_to_le32(src->d);
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}
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static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_map *virtio_gpu_map = data;
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return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev,
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virtio_gpu_map->handle,
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&virtio_gpu_map->offset);
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}
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static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
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struct list_head *head)
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{
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struct ttm_validate_buffer *buf;
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struct ttm_buffer_object *bo;
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struct virtio_gpu_object *qobj;
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int ret;
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ret = ttm_eu_reserve_buffers(ticket, head, true, NULL);
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if (ret != 0)
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return ret;
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list_for_each_entry(buf, head, head) {
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bo = buf->bo;
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qobj = container_of(bo, struct virtio_gpu_object, tbo);
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ret = ttm_bo_validate(bo, &qobj->placement, false, false);
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if (ret) {
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ttm_eu_backoff_reservation(ticket, head);
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return ret;
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}
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}
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return 0;
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}
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static void virtio_gpu_unref_list(struct list_head *head)
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{
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struct ttm_validate_buffer *buf;
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struct ttm_buffer_object *bo;
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struct virtio_gpu_object *qobj;
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list_for_each_entry(buf, head, head) {
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bo = buf->bo;
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qobj = container_of(bo, struct virtio_gpu_object, tbo);
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drm_gem_object_unreference_unlocked(&qobj->gem_base);
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}
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}
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/*
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* Usage of execbuffer:
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* Relocations need to take into account the full VIRTIO_GPUDrawable size.
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* However, the command as passed from user space must *not* contain the initial
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* VIRTIO_GPUReleaseInfo struct (first XXX bytes)
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*/
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static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
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struct drm_file *drm_file)
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{
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struct drm_virtgpu_execbuffer *exbuf = data;
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv;
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struct drm_gem_object *gobj;
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struct virtio_gpu_fence *fence;
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struct virtio_gpu_object *qobj;
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int ret;
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uint32_t *bo_handles = NULL;
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void __user *user_bo_handles = NULL;
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struct list_head validate_list;
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struct ttm_validate_buffer *buflist = NULL;
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int i;
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struct ww_acquire_ctx ticket;
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void *buf;
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if (vgdev->has_virgl_3d == false)
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return -ENOSYS;
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INIT_LIST_HEAD(&validate_list);
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if (exbuf->num_bo_handles) {
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bo_handles = drm_malloc_ab(exbuf->num_bo_handles,
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sizeof(uint32_t));
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buflist = drm_calloc_large(exbuf->num_bo_handles,
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sizeof(struct ttm_validate_buffer));
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if (!bo_handles || !buflist) {
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drm_free_large(bo_handles);
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drm_free_large(buflist);
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return -ENOMEM;
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}
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user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles;
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if (copy_from_user(bo_handles, user_bo_handles,
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exbuf->num_bo_handles * sizeof(uint32_t))) {
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ret = -EFAULT;
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drm_free_large(bo_handles);
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drm_free_large(buflist);
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return ret;
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}
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for (i = 0; i < exbuf->num_bo_handles; i++) {
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gobj = drm_gem_object_lookup(drm_file, bo_handles[i]);
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if (!gobj) {
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drm_free_large(bo_handles);
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drm_free_large(buflist);
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return -ENOENT;
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}
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qobj = gem_to_virtio_gpu_obj(gobj);
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buflist[i].bo = &qobj->tbo;
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list_add(&buflist[i].head, &validate_list);
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}
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drm_free_large(bo_handles);
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}
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ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
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if (ret)
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goto out_free;
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buf = memdup_user((void __user *)(uintptr_t)exbuf->command,
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exbuf->size);
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if (IS_ERR(buf)) {
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ret = PTR_ERR(buf);
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goto out_unresv;
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}
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virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
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vfpriv->ctx_id, &fence);
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ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
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/* fence the command bo */
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virtio_gpu_unref_list(&validate_list);
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drm_free_large(buflist);
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fence_put(&fence->f);
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return 0;
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out_unresv:
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ttm_eu_backoff_reservation(&ticket, &validate_list);
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out_free:
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virtio_gpu_unref_list(&validate_list);
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drm_free_large(buflist);
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return ret;
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}
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static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_getparam *param = data;
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int value;
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switch (param->param) {
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case VIRTGPU_PARAM_3D_FEATURES:
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value = vgdev->has_virgl_3d == true ? 1 : 0;
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break;
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case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
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value = 1;
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break;
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default:
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return -EINVAL;
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}
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if (copy_to_user((void __user *)(unsigned long)param->value,
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&value, sizeof(int))) {
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return -EFAULT;
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}
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return 0;
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}
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static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_resource_create *rc = data;
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int ret;
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uint32_t res_id;
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struct virtio_gpu_object *qobj;
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struct drm_gem_object *obj;
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uint32_t handle = 0;
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uint32_t size;
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struct list_head validate_list;
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struct ttm_validate_buffer mainbuf;
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struct virtio_gpu_fence *fence = NULL;
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struct ww_acquire_ctx ticket;
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struct virtio_gpu_resource_create_3d rc_3d;
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if (vgdev->has_virgl_3d == false) {
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if (rc->depth > 1)
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return -EINVAL;
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if (rc->nr_samples > 1)
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return -EINVAL;
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if (rc->last_level > 1)
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return -EINVAL;
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if (rc->target != 2)
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return -EINVAL;
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if (rc->array_size > 1)
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return -EINVAL;
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}
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INIT_LIST_HEAD(&validate_list);
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memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
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virtio_gpu_resource_id_get(vgdev, &res_id);
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size = rc->size;
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/* allocate a single page size object */
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if (size == 0)
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size = PAGE_SIZE;
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qobj = virtio_gpu_alloc_object(dev, size, false, false);
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if (IS_ERR(qobj)) {
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ret = PTR_ERR(qobj);
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goto fail_id;
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}
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obj = &qobj->gem_base;
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if (!vgdev->has_virgl_3d) {
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virtio_gpu_cmd_create_resource(vgdev, res_id, rc->format,
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rc->width, rc->height);
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ret = virtio_gpu_object_attach(vgdev, qobj, res_id, NULL);
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} else {
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/* use a gem reference since unref list undoes them */
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drm_gem_object_reference(&qobj->gem_base);
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mainbuf.bo = &qobj->tbo;
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list_add(&mainbuf.head, &validate_list);
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ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
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if (ret) {
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DRM_DEBUG("failed to validate\n");
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goto fail_unref;
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}
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rc_3d.resource_id = cpu_to_le32(res_id);
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rc_3d.target = cpu_to_le32(rc->target);
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rc_3d.format = cpu_to_le32(rc->format);
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rc_3d.bind = cpu_to_le32(rc->bind);
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rc_3d.width = cpu_to_le32(rc->width);
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rc_3d.height = cpu_to_le32(rc->height);
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rc_3d.depth = cpu_to_le32(rc->depth);
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rc_3d.array_size = cpu_to_le32(rc->array_size);
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rc_3d.last_level = cpu_to_le32(rc->last_level);
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rc_3d.nr_samples = cpu_to_le32(rc->nr_samples);
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rc_3d.flags = cpu_to_le32(rc->flags);
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virtio_gpu_cmd_resource_create_3d(vgdev, &rc_3d, NULL);
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ret = virtio_gpu_object_attach(vgdev, qobj, res_id, &fence);
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if (ret) {
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ttm_eu_backoff_reservation(&ticket, &validate_list);
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goto fail_unref;
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}
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ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
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}
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qobj->hw_res_handle = res_id;
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ret = drm_gem_handle_create(file_priv, obj, &handle);
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if (ret) {
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drm_gem_object_release(obj);
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if (vgdev->has_virgl_3d) {
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virtio_gpu_unref_list(&validate_list);
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fence_put(&fence->f);
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}
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return ret;
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}
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drm_gem_object_unreference_unlocked(obj);
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rc->res_handle = res_id; /* similiar to a VM address */
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rc->bo_handle = handle;
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if (vgdev->has_virgl_3d) {
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virtio_gpu_unref_list(&validate_list);
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fence_put(&fence->f);
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}
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return 0;
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fail_unref:
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if (vgdev->has_virgl_3d) {
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virtio_gpu_unref_list(&validate_list);
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fence_put(&fence->f);
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}
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//fail_obj:
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// drm_gem_object_handle_unreference_unlocked(obj);
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fail_id:
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virtio_gpu_resource_id_put(vgdev, res_id);
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return ret;
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}
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static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_virtgpu_resource_info *ri = data;
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struct drm_gem_object *gobj = NULL;
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struct virtio_gpu_object *qobj = NULL;
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gobj = drm_gem_object_lookup(file_priv, ri->bo_handle);
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if (gobj == NULL)
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return -ENOENT;
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qobj = gem_to_virtio_gpu_obj(gobj);
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ri->size = qobj->gem_base.size;
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ri->res_handle = qobj->hw_res_handle;
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drm_gem_object_unreference_unlocked(gobj);
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return 0;
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}
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static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
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void *data,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct drm_virtgpu_3d_transfer_from_host *args = data;
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struct drm_gem_object *gobj = NULL;
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struct virtio_gpu_object *qobj = NULL;
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struct virtio_gpu_fence *fence;
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int ret;
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u32 offset = args->offset;
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struct virtio_gpu_box box;
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if (vgdev->has_virgl_3d == false)
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return -ENOSYS;
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gobj = drm_gem_object_lookup(file, args->bo_handle);
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if (gobj == NULL)
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return -ENOENT;
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qobj = gem_to_virtio_gpu_obj(gobj);
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ret = virtio_gpu_object_reserve(qobj, false);
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if (ret)
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goto out;
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ret = ttm_bo_validate(&qobj->tbo, &qobj->placement,
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true, false);
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if (unlikely(ret))
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goto out_unres;
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convert_to_hw_box(&box, &args->box);
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virtio_gpu_cmd_transfer_from_host_3d
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(vgdev, qobj->hw_res_handle,
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vfpriv->ctx_id, offset, args->level,
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&box, &fence);
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reservation_object_add_excl_fence(qobj->tbo.resv,
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&fence->f);
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fence_put(&fence->f);
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out_unres:
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virtio_gpu_object_unreserve(qobj);
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out:
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drm_gem_object_unreference_unlocked(gobj);
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return ret;
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}
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static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
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struct drm_virtgpu_3d_transfer_to_host *args = data;
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struct drm_gem_object *gobj = NULL;
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struct virtio_gpu_object *qobj = NULL;
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struct virtio_gpu_fence *fence;
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struct virtio_gpu_box box;
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int ret;
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u32 offset = args->offset;
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gobj = drm_gem_object_lookup(file, args->bo_handle);
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if (gobj == NULL)
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return -ENOENT;
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qobj = gem_to_virtio_gpu_obj(gobj);
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ret = virtio_gpu_object_reserve(qobj, false);
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if (ret)
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goto out;
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ret = ttm_bo_validate(&qobj->tbo, &qobj->placement,
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true, false);
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if (unlikely(ret))
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goto out_unres;
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convert_to_hw_box(&box, &args->box);
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if (!vgdev->has_virgl_3d) {
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virtio_gpu_cmd_transfer_to_host_2d
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(vgdev, qobj->hw_res_handle, offset,
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box.w, box.h, box.x, box.y, NULL);
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} else {
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virtio_gpu_cmd_transfer_to_host_3d
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(vgdev, qobj->hw_res_handle,
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vfpriv ? vfpriv->ctx_id : 0, offset,
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args->level, &box, &fence);
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reservation_object_add_excl_fence(qobj->tbo.resv,
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&fence->f);
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fence_put(&fence->f);
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}
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out_unres:
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virtio_gpu_object_unreserve(qobj);
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out:
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drm_gem_object_unreference_unlocked(gobj);
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return ret;
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}
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static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file)
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{
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struct drm_virtgpu_3d_wait *args = data;
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struct drm_gem_object *gobj = NULL;
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struct virtio_gpu_object *qobj = NULL;
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int ret;
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bool nowait = false;
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gobj = drm_gem_object_lookup(file, args->handle);
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if (gobj == NULL)
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return -ENOENT;
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qobj = gem_to_virtio_gpu_obj(gobj);
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if (args->flags & VIRTGPU_WAIT_NOWAIT)
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nowait = true;
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ret = virtio_gpu_object_wait(qobj, nowait);
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drm_gem_object_unreference_unlocked(gobj);
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return ret;
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}
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static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
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void *data, struct drm_file *file)
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{
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct drm_virtgpu_get_caps *args = data;
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unsigned size, host_caps_size;
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int i;
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int found_valid = -1;
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int ret;
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struct virtio_gpu_drv_cap_cache *cache_ent;
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void *ptr;
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if (vgdev->num_capsets == 0)
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return -ENOSYS;
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/* don't allow userspace to pass 0 */
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if (args->size == 0)
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return -EINVAL;
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|
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spin_lock(&vgdev->display_info_lock);
|
|
for (i = 0; i < vgdev->num_capsets; i++) {
|
|
if (vgdev->capsets[i].id == args->cap_set_id) {
|
|
if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
|
|
found_valid = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (found_valid == -1) {
|
|
spin_unlock(&vgdev->display_info_lock);
|
|
return -EINVAL;
|
|
}
|
|
|
|
host_caps_size = vgdev->capsets[found_valid].max_size;
|
|
/* only copy to user the minimum of the host caps size or the guest caps size */
|
|
size = min(args->size, host_caps_size);
|
|
|
|
list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
|
|
if (cache_ent->id == args->cap_set_id &&
|
|
cache_ent->version == args->cap_set_ver) {
|
|
ptr = cache_ent->caps_cache;
|
|
spin_unlock(&vgdev->display_info_lock);
|
|
goto copy_exit;
|
|
}
|
|
}
|
|
spin_unlock(&vgdev->display_info_lock);
|
|
|
|
/* not in cache - need to talk to hw */
|
|
virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
|
|
&cache_ent);
|
|
|
|
ret = wait_event_timeout(vgdev->resp_wq,
|
|
atomic_read(&cache_ent->is_valid), 5 * HZ);
|
|
|
|
/* is_valid check must proceed before copy of the cache entry. */
|
|
smp_rmb();
|
|
|
|
ptr = cache_ent->caps_cache;
|
|
|
|
copy_exit:
|
|
if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
|
|
virtio_gpu_resource_create_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
|
|
/* make transfer async to the main ring? - no sure, can we
|
|
thread these in the underlying GL */
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
|
|
virtio_gpu_transfer_from_host_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
|
|
virtio_gpu_transfer_to_host_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
|
|
DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
};
|