1174 lines
27 KiB
C
1174 lines
27 KiB
C
/*
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* mISDNinfineon.c
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* Support for cards based on following Infineon ISDN chipsets
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* - ISAC + HSCX
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* - IPAC and IPAC-X
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* - ISAC-SX + HSCX
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*
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* Supported cards:
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* - Dialogic Diva 2.0
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* - Dialogic Diva 2.0U
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* - Dialogic Diva 2.01
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* - Dialogic Diva 2.02
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* - Sedlbauer Speedwin
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* - HST Saphir3
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* - Develo (former ELSA) Microlink PCI (Quickstep 1000)
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* - Develo (former ELSA) Quickstep 3000
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* - Berkom Scitel BRIX Quadro
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* - Dr.Neuhaus (Sagem) Niccy
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*
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*
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*
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* Author Karsten Keil <keil@isdn4linux.de>
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*
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* Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/mISDNhw.h>
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#include <linux/slab.h>
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#include "ipac.h"
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#define INFINEON_REV "1.0"
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static int inf_cnt;
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static u32 debug;
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static u32 irqloops = 4;
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enum inf_types {
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INF_NONE,
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INF_DIVA20,
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INF_DIVA20U,
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INF_DIVA201,
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INF_DIVA202,
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INF_SPEEDWIN,
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INF_SAPHIR3,
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INF_QS1000,
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INF_QS3000,
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INF_NICCY,
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INF_SCT_1,
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INF_SCT_2,
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INF_SCT_3,
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INF_SCT_4,
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INF_GAZEL_R685,
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INF_GAZEL_R753
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};
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enum addr_mode {
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AM_NONE = 0,
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AM_IO,
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AM_MEMIO,
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AM_IND_IO,
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};
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struct inf_cinfo {
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enum inf_types typ;
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const char *full;
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const char *name;
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enum addr_mode cfg_mode;
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enum addr_mode addr_mode;
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u8 cfg_bar;
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u8 addr_bar;
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void *irqfunc;
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};
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struct _ioaddr {
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enum addr_mode mode;
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union {
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void __iomem *p;
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struct _ioport io;
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} a;
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};
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struct _iohandle {
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enum addr_mode mode;
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resource_size_t size;
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resource_size_t start;
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void __iomem *p;
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};
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struct inf_hw {
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struct list_head list;
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struct pci_dev *pdev;
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const struct inf_cinfo *ci;
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char name[MISDN_MAX_IDLEN];
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u32 irq;
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u32 irqcnt;
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struct _iohandle cfg;
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struct _iohandle addr;
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struct _ioaddr isac;
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struct _ioaddr hscx;
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spinlock_t lock; /* HW access lock */
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struct ipac_hw ipac;
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struct inf_hw *sc[3]; /* slave cards */
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};
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#define PCI_SUBVENDOR_HST_SAPHIR3 0x52
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#define PCI_SUBVENDOR_SEDLBAUER_PCI 0x53
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#define PCI_SUB_ID_SEDLBAUER 0x01
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static struct pci_device_id infineon_ids[] = {
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{ PCI_VDEVICE(EICON, PCI_DEVICE_ID_EICON_DIVA20), INF_DIVA20 },
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{ PCI_VDEVICE(EICON, PCI_DEVICE_ID_EICON_DIVA20_U), INF_DIVA20U },
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{ PCI_VDEVICE(EICON, PCI_DEVICE_ID_EICON_DIVA201), INF_DIVA201 },
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{ PCI_VDEVICE(EICON, PCI_DEVICE_ID_EICON_DIVA202), INF_DIVA202 },
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{ PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_100,
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PCI_SUBVENDOR_SEDLBAUER_PCI, PCI_SUB_ID_SEDLBAUER, 0, 0,
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INF_SPEEDWIN },
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{ PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_100,
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PCI_SUBVENDOR_HST_SAPHIR3, PCI_SUB_ID_SEDLBAUER, 0, 0, INF_SAPHIR3 },
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{ PCI_VDEVICE(ELSA, PCI_DEVICE_ID_ELSA_MICROLINK), INF_QS1000 },
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{ PCI_VDEVICE(ELSA, PCI_DEVICE_ID_ELSA_QS3000), INF_QS3000 },
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{ PCI_VDEVICE(SATSAGEM, PCI_DEVICE_ID_SATSAGEM_NICCY), INF_NICCY },
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{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
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PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO, 0, 0,
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INF_SCT_1 },
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{ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_R685), INF_GAZEL_R685 },
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{ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_R753), INF_GAZEL_R753 },
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{ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_DJINN_ITOO), INF_GAZEL_R753 },
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{ PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_OLITEC), INF_GAZEL_R753 },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, infineon_ids);
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/* PCI interface specific defines */
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/* Diva 2.0/2.0U */
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#define DIVA_HSCX_PORT 0x00
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#define DIVA_HSCX_ALE 0x04
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#define DIVA_ISAC_PORT 0x08
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#define DIVA_ISAC_ALE 0x0C
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#define DIVA_PCI_CTRL 0x10
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/* DIVA_PCI_CTRL bits */
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#define DIVA_IRQ_BIT 0x01
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#define DIVA_RESET_BIT 0x08
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#define DIVA_EEPROM_CLK 0x40
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#define DIVA_LED_A 0x10
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#define DIVA_LED_B 0x20
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#define DIVA_IRQ_CLR 0x80
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/* Diva 2.01/2.02 */
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/* Siemens PITA */
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#define PITA_ICR_REG 0x00
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#define PITA_INT0_STATUS 0x02
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#define PITA_MISC_REG 0x1c
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#define PITA_PARA_SOFTRESET 0x01000000
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#define PITA_SER_SOFTRESET 0x02000000
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#define PITA_PARA_MPX_MODE 0x04000000
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#define PITA_INT0_ENABLE 0x00020000
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/* TIGER 100 Registers */
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#define TIGER_RESET_ADDR 0x00
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#define TIGER_EXTERN_RESET 0x01
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#define TIGER_AUX_CTRL 0x02
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#define TIGER_AUX_DATA 0x03
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#define TIGER_AUX_IRQMASK 0x05
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#define TIGER_AUX_STATUS 0x07
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/* Tiger AUX BITs */
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#define TIGER_IOMASK 0xdd /* 1 and 5 are inputs */
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#define TIGER_IRQ_BIT 0x02
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#define TIGER_IPAC_ALE 0xC0
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#define TIGER_IPAC_PORT 0xC8
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/* ELSA (now Develo) PCI cards */
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#define ELSA_IRQ_ADDR 0x4c
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#define ELSA_IRQ_MASK 0x04
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#define QS1000_IRQ_OFF 0x01
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#define QS3000_IRQ_OFF 0x03
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#define QS1000_IRQ_ON 0x41
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#define QS3000_IRQ_ON 0x43
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/* Dr Neuhaus/Sagem Niccy */
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#define NICCY_ISAC_PORT 0x00
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#define NICCY_HSCX_PORT 0x01
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#define NICCY_ISAC_ALE 0x02
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#define NICCY_HSCX_ALE 0x03
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#define NICCY_IRQ_CTRL_REG 0x38
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#define NICCY_IRQ_ENABLE 0x001f00
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#define NICCY_IRQ_DISABLE 0xff0000
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#define NICCY_IRQ_BIT 0x800000
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/* Scitel PLX */
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#define SCT_PLX_IRQ_ADDR 0x4c
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#define SCT_PLX_RESET_ADDR 0x50
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#define SCT_PLX_IRQ_ENABLE 0x41
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#define SCT_PLX_RESET_BIT 0x04
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/* Gazel */
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#define GAZEL_IPAC_DATA_PORT 0x04
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/* Gazel PLX */
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#define GAZEL_CNTRL 0x50
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#define GAZEL_RESET 0x04
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#define GAZEL_RESET_9050 0x40000000
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#define GAZEL_INCSR 0x4C
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#define GAZEL_ISAC_EN 0x08
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#define GAZEL_INT_ISAC 0x20
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#define GAZEL_HSCX_EN 0x01
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#define GAZEL_INT_HSCX 0x04
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#define GAZEL_PCI_EN 0x40
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#define GAZEL_IPAC_EN 0x03
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static LIST_HEAD(Cards);
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static DEFINE_RWLOCK(card_lock); /* protect Cards */
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static void
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_set_debug(struct inf_hw *card)
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{
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card->ipac.isac.dch.debug = debug;
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card->ipac.hscx[0].bch.debug = debug;
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card->ipac.hscx[1].bch.debug = debug;
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}
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static int
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set_debug(const char *val, const struct kernel_param *kp)
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{
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int ret;
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struct inf_hw *card;
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ret = param_set_uint(val, kp);
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if (!ret) {
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read_lock(&card_lock);
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list_for_each_entry(card, &Cards, list)
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_set_debug(card);
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read_unlock(&card_lock);
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}
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return ret;
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}
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MODULE_AUTHOR("Karsten Keil");
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MODULE_LICENSE("GPL v2");
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MODULE_VERSION(INFINEON_REV);
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module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(debug, "infineon debug mask");
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module_param(irqloops, uint, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(irqloops, "infineon maximal irqloops (default 4)");
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/* Interface functions */
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IOFUNC_IO(ISAC, inf_hw, isac.a.io)
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IOFUNC_IO(IPAC, inf_hw, hscx.a.io)
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IOFUNC_IND(ISAC, inf_hw, isac.a.io)
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IOFUNC_IND(IPAC, inf_hw, hscx.a.io)
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IOFUNC_MEMIO(ISAC, inf_hw, u32, isac.a.p)
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IOFUNC_MEMIO(IPAC, inf_hw, u32, hscx.a.p)
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static irqreturn_t
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diva_irq(int intno, void *dev_id)
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{
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struct inf_hw *hw = dev_id;
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u8 val;
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spin_lock(&hw->lock);
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val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL);
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if (!(val & DIVA_IRQ_BIT)) { /* for us or shared ? */
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spin_unlock(&hw->lock);
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return IRQ_NONE; /* shared */
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}
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hw->irqcnt++;
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mISDNipac_irq(&hw->ipac, irqloops);
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spin_unlock(&hw->lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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diva20x_irq(int intno, void *dev_id)
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{
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struct inf_hw *hw = dev_id;
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u8 val;
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spin_lock(&hw->lock);
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val = readb(hw->cfg.p);
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if (!(val & PITA_INT0_STATUS)) { /* for us or shared ? */
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spin_unlock(&hw->lock);
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return IRQ_NONE; /* shared */
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}
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hw->irqcnt++;
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mISDNipac_irq(&hw->ipac, irqloops);
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writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */
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spin_unlock(&hw->lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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tiger_irq(int intno, void *dev_id)
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{
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struct inf_hw *hw = dev_id;
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u8 val;
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spin_lock(&hw->lock);
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val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS);
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if (val & TIGER_IRQ_BIT) { /* for us or shared ? */
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spin_unlock(&hw->lock);
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return IRQ_NONE; /* shared */
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}
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hw->irqcnt++;
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mISDNipac_irq(&hw->ipac, irqloops);
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spin_unlock(&hw->lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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elsa_irq(int intno, void *dev_id)
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{
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struct inf_hw *hw = dev_id;
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u8 val;
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spin_lock(&hw->lock);
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val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR);
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if (!(val & ELSA_IRQ_MASK)) {
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spin_unlock(&hw->lock);
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return IRQ_NONE; /* shared */
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}
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hw->irqcnt++;
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mISDNipac_irq(&hw->ipac, irqloops);
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spin_unlock(&hw->lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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niccy_irq(int intno, void *dev_id)
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{
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struct inf_hw *hw = dev_id;
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u32 val;
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spin_lock(&hw->lock);
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val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
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if (!(val & NICCY_IRQ_BIT)) { /* for us or shared ? */
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spin_unlock(&hw->lock);
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return IRQ_NONE; /* shared */
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}
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outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
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hw->irqcnt++;
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mISDNipac_irq(&hw->ipac, irqloops);
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spin_unlock(&hw->lock);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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gazel_irq(int intno, void *dev_id)
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{
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struct inf_hw *hw = dev_id;
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irqreturn_t ret;
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spin_lock(&hw->lock);
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ret = mISDNipac_irq(&hw->ipac, irqloops);
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spin_unlock(&hw->lock);
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return ret;
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}
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static irqreturn_t
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ipac_irq(int intno, void *dev_id)
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{
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struct inf_hw *hw = dev_id;
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u8 val;
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spin_lock(&hw->lock);
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val = hw->ipac.read_reg(hw, IPAC_ISTA);
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if (!(val & 0x3f)) {
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spin_unlock(&hw->lock);
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return IRQ_NONE; /* shared */
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}
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hw->irqcnt++;
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mISDNipac_irq(&hw->ipac, irqloops);
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spin_unlock(&hw->lock);
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return IRQ_HANDLED;
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}
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static void
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enable_hwirq(struct inf_hw *hw)
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{
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u16 w;
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u32 val;
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switch (hw->ci->typ) {
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case INF_DIVA201:
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case INF_DIVA202:
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writel(PITA_INT0_ENABLE, hw->cfg.p);
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break;
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case INF_SPEEDWIN:
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case INF_SAPHIR3:
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outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
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break;
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case INF_QS1000:
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outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
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break;
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case INF_QS3000:
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outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
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break;
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case INF_NICCY:
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val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
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val |= NICCY_IRQ_ENABLE;
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outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
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break;
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case INF_SCT_1:
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w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
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w |= SCT_PLX_IRQ_ENABLE;
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outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
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break;
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case INF_GAZEL_R685:
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outb(GAZEL_ISAC_EN + GAZEL_HSCX_EN + GAZEL_PCI_EN,
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(u32)hw->cfg.start + GAZEL_INCSR);
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break;
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case INF_GAZEL_R753:
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outb(GAZEL_IPAC_EN + GAZEL_PCI_EN,
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(u32)hw->cfg.start + GAZEL_INCSR);
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break;
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default:
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break;
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}
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}
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static void
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disable_hwirq(struct inf_hw *hw)
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{
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u16 w;
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u32 val;
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switch (hw->ci->typ) {
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case INF_DIVA201:
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case INF_DIVA202:
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writel(0, hw->cfg.p);
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break;
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case INF_SPEEDWIN:
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case INF_SAPHIR3:
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outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
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break;
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case INF_QS1000:
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outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
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break;
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case INF_QS3000:
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outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
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break;
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case INF_NICCY:
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val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
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val &= NICCY_IRQ_DISABLE;
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outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
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break;
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case INF_SCT_1:
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w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
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w &= (~SCT_PLX_IRQ_ENABLE);
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outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
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break;
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case INF_GAZEL_R685:
|
|
case INF_GAZEL_R753:
|
|
outb(0, (u32)hw->cfg.start + GAZEL_INCSR);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void
|
|
ipac_chip_reset(struct inf_hw *hw)
|
|
{
|
|
hw->ipac.write_reg(hw, IPAC_POTA2, 0x20);
|
|
mdelay(5);
|
|
hw->ipac.write_reg(hw, IPAC_POTA2, 0x00);
|
|
mdelay(5);
|
|
hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf);
|
|
hw->ipac.write_reg(hw, IPAC_MASK, 0xc0);
|
|
}
|
|
|
|
static void
|
|
reset_inf(struct inf_hw *hw)
|
|
{
|
|
u16 w;
|
|
u32 val;
|
|
|
|
if (debug & DEBUG_HW)
|
|
pr_notice("%s: resetting card\n", hw->name);
|
|
switch (hw->ci->typ) {
|
|
case INF_DIVA20:
|
|
case INF_DIVA20U:
|
|
outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL);
|
|
mdelay(10);
|
|
outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL);
|
|
mdelay(10);
|
|
/* Workaround PCI9060 */
|
|
outb(9, (u32)hw->cfg.start + 0x69);
|
|
outb(DIVA_RESET_BIT | DIVA_LED_A,
|
|
(u32)hw->cfg.start + DIVA_PCI_CTRL);
|
|
break;
|
|
case INF_DIVA201:
|
|
writel(PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE,
|
|
hw->cfg.p + PITA_MISC_REG);
|
|
mdelay(1);
|
|
writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG);
|
|
mdelay(10);
|
|
break;
|
|
case INF_DIVA202:
|
|
writel(PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE,
|
|
hw->cfg.p + PITA_MISC_REG);
|
|
mdelay(1);
|
|
writel(PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET,
|
|
hw->cfg.p + PITA_MISC_REG);
|
|
mdelay(10);
|
|
break;
|
|
case INF_SPEEDWIN:
|
|
case INF_SAPHIR3:
|
|
ipac_chip_reset(hw);
|
|
hw->ipac.write_reg(hw, IPAC_ACFG, 0xff);
|
|
hw->ipac.write_reg(hw, IPAC_AOE, 0x00);
|
|
hw->ipac.write_reg(hw, IPAC_PCFG, 0x12);
|
|
break;
|
|
case INF_QS1000:
|
|
case INF_QS3000:
|
|
ipac_chip_reset(hw);
|
|
hw->ipac.write_reg(hw, IPAC_ACFG, 0x00);
|
|
hw->ipac.write_reg(hw, IPAC_AOE, 0x3c);
|
|
hw->ipac.write_reg(hw, IPAC_ATX, 0xff);
|
|
break;
|
|
case INF_NICCY:
|
|
break;
|
|
case INF_SCT_1:
|
|
w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
|
|
w &= (~SCT_PLX_RESET_BIT);
|
|
outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
|
|
mdelay(10);
|
|
w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
|
|
w |= SCT_PLX_RESET_BIT;
|
|
outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
|
|
mdelay(10);
|
|
break;
|
|
case INF_GAZEL_R685:
|
|
val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
|
|
val |= (GAZEL_RESET_9050 + GAZEL_RESET);
|
|
outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
|
|
val &= ~(GAZEL_RESET_9050 + GAZEL_RESET);
|
|
mdelay(4);
|
|
outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
|
|
mdelay(10);
|
|
hw->ipac.isac.adf2 = 0x87;
|
|
hw->ipac.hscx[0].slot = 0x1f;
|
|
hw->ipac.hscx[1].slot = 0x23;
|
|
break;
|
|
case INF_GAZEL_R753:
|
|
val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
|
|
val |= (GAZEL_RESET_9050 + GAZEL_RESET);
|
|
outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
|
|
val &= ~(GAZEL_RESET_9050 + GAZEL_RESET);
|
|
mdelay(4);
|
|
outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
|
|
mdelay(10);
|
|
ipac_chip_reset(hw);
|
|
hw->ipac.write_reg(hw, IPAC_ACFG, 0xff);
|
|
hw->ipac.write_reg(hw, IPAC_AOE, 0x00);
|
|
hw->ipac.conf = 0x01; /* IOM off */
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
enable_hwirq(hw);
|
|
}
|
|
|
|
static int
|
|
inf_ctrl(struct inf_hw *hw, u32 cmd, u_long arg)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (cmd) {
|
|
case HW_RESET_REQ:
|
|
reset_inf(hw);
|
|
break;
|
|
default:
|
|
pr_info("%s: %s unknown command %x %lx\n",
|
|
hw->name, __func__, cmd, arg);
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
init_irq(struct inf_hw *hw)
|
|
{
|
|
int ret, cnt = 3;
|
|
u_long flags;
|
|
|
|
if (!hw->ci->irqfunc)
|
|
return -EINVAL;
|
|
ret = request_irq(hw->irq, hw->ci->irqfunc, IRQF_SHARED, hw->name, hw);
|
|
if (ret) {
|
|
pr_info("%s: couldn't get interrupt %d\n", hw->name, hw->irq);
|
|
return ret;
|
|
}
|
|
while (cnt--) {
|
|
spin_lock_irqsave(&hw->lock, flags);
|
|
reset_inf(hw);
|
|
ret = hw->ipac.init(&hw->ipac);
|
|
if (ret) {
|
|
spin_unlock_irqrestore(&hw->lock, flags);
|
|
pr_info("%s: ISAC init failed with %d\n",
|
|
hw->name, ret);
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&hw->lock, flags);
|
|
msleep_interruptible(10);
|
|
if (debug & DEBUG_HW)
|
|
pr_notice("%s: IRQ %d count %d\n", hw->name,
|
|
hw->irq, hw->irqcnt);
|
|
if (!hw->irqcnt) {
|
|
pr_info("%s: IRQ(%d) got no requests during init %d\n",
|
|
hw->name, hw->irq, 3 - cnt);
|
|
} else
|
|
return 0;
|
|
}
|
|
free_irq(hw->irq, hw);
|
|
return -EIO;
|
|
}
|
|
|
|
static void
|
|
release_io(struct inf_hw *hw)
|
|
{
|
|
if (hw->cfg.mode) {
|
|
if (hw->cfg.p) {
|
|
release_mem_region(hw->cfg.start, hw->cfg.size);
|
|
iounmap(hw->cfg.p);
|
|
} else
|
|
release_region(hw->cfg.start, hw->cfg.size);
|
|
hw->cfg.mode = AM_NONE;
|
|
}
|
|
if (hw->addr.mode) {
|
|
if (hw->addr.p) {
|
|
release_mem_region(hw->addr.start, hw->addr.size);
|
|
iounmap(hw->addr.p);
|
|
} else
|
|
release_region(hw->addr.start, hw->addr.size);
|
|
hw->addr.mode = AM_NONE;
|
|
}
|
|
}
|
|
|
|
static int
|
|
setup_io(struct inf_hw *hw)
|
|
{
|
|
int err = 0;
|
|
|
|
if (hw->ci->cfg_mode) {
|
|
hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar);
|
|
hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar);
|
|
if (hw->ci->cfg_mode == AM_MEMIO) {
|
|
if (!request_mem_region(hw->cfg.start, hw->cfg.size,
|
|
hw->name))
|
|
err = -EBUSY;
|
|
} else {
|
|
if (!request_region(hw->cfg.start, hw->cfg.size,
|
|
hw->name))
|
|
err = -EBUSY;
|
|
}
|
|
if (err) {
|
|
pr_info("mISDN: %s config port %lx (%lu bytes)"
|
|
"already in use\n", hw->name,
|
|
(ulong)hw->cfg.start, (ulong)hw->cfg.size);
|
|
return err;
|
|
}
|
|
if (hw->ci->cfg_mode == AM_MEMIO)
|
|
hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size);
|
|
hw->cfg.mode = hw->ci->cfg_mode;
|
|
if (debug & DEBUG_HW)
|
|
pr_notice("%s: IO cfg %lx (%lu bytes) mode%d\n",
|
|
hw->name, (ulong)hw->cfg.start,
|
|
(ulong)hw->cfg.size, hw->ci->cfg_mode);
|
|
|
|
}
|
|
if (hw->ci->addr_mode) {
|
|
hw->addr.start = pci_resource_start(hw->pdev, hw->ci->addr_bar);
|
|
hw->addr.size = pci_resource_len(hw->pdev, hw->ci->addr_bar);
|
|
if (hw->ci->addr_mode == AM_MEMIO) {
|
|
if (!request_mem_region(hw->addr.start, hw->addr.size,
|
|
hw->name))
|
|
err = -EBUSY;
|
|
} else {
|
|
if (!request_region(hw->addr.start, hw->addr.size,
|
|
hw->name))
|
|
err = -EBUSY;
|
|
}
|
|
if (err) {
|
|
pr_info("mISDN: %s address port %lx (%lu bytes)"
|
|
"already in use\n", hw->name,
|
|
(ulong)hw->addr.start, (ulong)hw->addr.size);
|
|
return err;
|
|
}
|
|
if (hw->ci->addr_mode == AM_MEMIO)
|
|
hw->addr.p = ioremap(hw->addr.start, hw->addr.size);
|
|
hw->addr.mode = hw->ci->addr_mode;
|
|
if (debug & DEBUG_HW)
|
|
pr_notice("%s: IO addr %lx (%lu bytes) mode%d\n",
|
|
hw->name, (ulong)hw->addr.start,
|
|
(ulong)hw->addr.size, hw->ci->addr_mode);
|
|
|
|
}
|
|
|
|
switch (hw->ci->typ) {
|
|
case INF_DIVA20:
|
|
case INF_DIVA20U:
|
|
hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
|
|
hw->isac.mode = hw->cfg.mode;
|
|
hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE;
|
|
hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT;
|
|
hw->hscx.mode = hw->cfg.mode;
|
|
hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE;
|
|
hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT;
|
|
break;
|
|
case INF_DIVA201:
|
|
hw->ipac.type = IPAC_TYPE_IPAC;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->isac.a.p = hw->addr.p;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
hw->hscx.a.p = hw->addr.p;
|
|
break;
|
|
case INF_DIVA202:
|
|
hw->ipac.type = IPAC_TYPE_IPACX;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->isac.a.p = hw->addr.p;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
hw->hscx.a.p = hw->addr.p;
|
|
break;
|
|
case INF_SPEEDWIN:
|
|
case INF_SAPHIR3:
|
|
hw->ipac.type = IPAC_TYPE_IPAC;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.mode = hw->cfg.mode;
|
|
hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
|
|
hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
|
|
hw->hscx.mode = hw->cfg.mode;
|
|
hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
|
|
hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
|
|
outb(0xff, (ulong)hw->cfg.start);
|
|
mdelay(1);
|
|
outb(0x00, (ulong)hw->cfg.start);
|
|
mdelay(1);
|
|
outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL);
|
|
break;
|
|
case INF_QS1000:
|
|
case INF_QS3000:
|
|
hw->ipac.type = IPAC_TYPE_IPAC;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.a.io.ale = (u32)hw->addr.start;
|
|
hw->isac.a.io.port = (u32)hw->addr.start + 1;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->hscx.a.io.ale = (u32)hw->addr.start;
|
|
hw->hscx.a.io.port = (u32)hw->addr.start + 1;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
break;
|
|
case INF_NICCY:
|
|
hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->isac.a.io.ale = (u32)hw->addr.start + NICCY_ISAC_ALE;
|
|
hw->isac.a.io.port = (u32)hw->addr.start + NICCY_ISAC_PORT;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE;
|
|
hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT;
|
|
break;
|
|
case INF_SCT_1:
|
|
hw->ipac.type = IPAC_TYPE_IPAC;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.a.io.ale = (u32)hw->addr.start;
|
|
hw->isac.a.io.port = hw->isac.a.io.ale + 4;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->hscx.a.io.ale = hw->isac.a.io.ale;
|
|
hw->hscx.a.io.port = hw->isac.a.io.port;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
break;
|
|
case INF_SCT_2:
|
|
hw->ipac.type = IPAC_TYPE_IPAC;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.a.io.ale = (u32)hw->addr.start + 0x08;
|
|
hw->isac.a.io.port = hw->isac.a.io.ale + 4;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->hscx.a.io.ale = hw->isac.a.io.ale;
|
|
hw->hscx.a.io.port = hw->isac.a.io.port;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
break;
|
|
case INF_SCT_3:
|
|
hw->ipac.type = IPAC_TYPE_IPAC;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.a.io.ale = (u32)hw->addr.start + 0x10;
|
|
hw->isac.a.io.port = hw->isac.a.io.ale + 4;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->hscx.a.io.ale = hw->isac.a.io.ale;
|
|
hw->hscx.a.io.port = hw->isac.a.io.port;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
break;
|
|
case INF_SCT_4:
|
|
hw->ipac.type = IPAC_TYPE_IPAC;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.a.io.ale = (u32)hw->addr.start + 0x20;
|
|
hw->isac.a.io.port = hw->isac.a.io.ale + 4;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->hscx.a.io.ale = hw->isac.a.io.ale;
|
|
hw->hscx.a.io.port = hw->isac.a.io.port;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
break;
|
|
case INF_GAZEL_R685:
|
|
hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->isac.a.io.port = (u32)hw->addr.start;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
hw->hscx.a.io.port = hw->isac.a.io.port;
|
|
break;
|
|
case INF_GAZEL_R753:
|
|
hw->ipac.type = IPAC_TYPE_IPAC;
|
|
hw->ipac.isac.off = 0x80;
|
|
hw->isac.mode = hw->addr.mode;
|
|
hw->isac.a.io.ale = (u32)hw->addr.start;
|
|
hw->isac.a.io.port = (u32)hw->addr.start + GAZEL_IPAC_DATA_PORT;
|
|
hw->hscx.mode = hw->addr.mode;
|
|
hw->hscx.a.io.ale = hw->isac.a.io.ale;
|
|
hw->hscx.a.io.port = hw->isac.a.io.port;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
switch (hw->isac.mode) {
|
|
case AM_MEMIO:
|
|
ASSIGN_FUNC_IPAC(MIO, hw->ipac);
|
|
break;
|
|
case AM_IND_IO:
|
|
ASSIGN_FUNC_IPAC(IND, hw->ipac);
|
|
break;
|
|
case AM_IO:
|
|
ASSIGN_FUNC_IPAC(IO, hw->ipac);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
release_card(struct inf_hw *card) {
|
|
ulong flags;
|
|
int i;
|
|
|
|
spin_lock_irqsave(&card->lock, flags);
|
|
disable_hwirq(card);
|
|
spin_unlock_irqrestore(&card->lock, flags);
|
|
card->ipac.isac.release(&card->ipac.isac);
|
|
free_irq(card->irq, card);
|
|
mISDN_unregister_device(&card->ipac.isac.dch.dev);
|
|
release_io(card);
|
|
write_lock_irqsave(&card_lock, flags);
|
|
list_del(&card->list);
|
|
write_unlock_irqrestore(&card_lock, flags);
|
|
switch (card->ci->typ) {
|
|
case INF_SCT_2:
|
|
case INF_SCT_3:
|
|
case INF_SCT_4:
|
|
break;
|
|
case INF_SCT_1:
|
|
for (i = 0; i < 3; i++) {
|
|
if (card->sc[i])
|
|
release_card(card->sc[i]);
|
|
card->sc[i] = NULL;
|
|
}
|
|
default:
|
|
pci_disable_device(card->pdev);
|
|
pci_set_drvdata(card->pdev, NULL);
|
|
break;
|
|
}
|
|
kfree(card);
|
|
inf_cnt--;
|
|
}
|
|
|
|
static int
|
|
setup_instance(struct inf_hw *card)
|
|
{
|
|
int err;
|
|
ulong flags;
|
|
|
|
snprintf(card->name, MISDN_MAX_IDLEN - 1, "%s.%d", card->ci->name,
|
|
inf_cnt + 1);
|
|
write_lock_irqsave(&card_lock, flags);
|
|
list_add_tail(&card->list, &Cards);
|
|
write_unlock_irqrestore(&card_lock, flags);
|
|
|
|
_set_debug(card);
|
|
card->ipac.isac.name = card->name;
|
|
card->ipac.name = card->name;
|
|
card->ipac.owner = THIS_MODULE;
|
|
spin_lock_init(&card->lock);
|
|
card->ipac.isac.hwlock = &card->lock;
|
|
card->ipac.hwlock = &card->lock;
|
|
card->ipac.ctrl = (void *)&inf_ctrl;
|
|
|
|
err = setup_io(card);
|
|
if (err)
|
|
goto error_setup;
|
|
|
|
card->ipac.isac.dch.dev.Bprotocols =
|
|
mISDNipac_init(&card->ipac, card);
|
|
|
|
if (card->ipac.isac.dch.dev.Bprotocols == 0)
|
|
goto error_setup;
|
|
|
|
err = mISDN_register_device(&card->ipac.isac.dch.dev,
|
|
&card->pdev->dev, card->name);
|
|
if (err)
|
|
goto error;
|
|
|
|
err = init_irq(card);
|
|
if (!err) {
|
|
inf_cnt++;
|
|
pr_notice("Infineon %d cards installed\n", inf_cnt);
|
|
return 0;
|
|
}
|
|
mISDN_unregister_device(&card->ipac.isac.dch.dev);
|
|
error:
|
|
card->ipac.release(&card->ipac);
|
|
error_setup:
|
|
release_io(card);
|
|
write_lock_irqsave(&card_lock, flags);
|
|
list_del(&card->list);
|
|
write_unlock_irqrestore(&card_lock, flags);
|
|
return err;
|
|
}
|
|
|
|
static const struct inf_cinfo inf_card_info[] = {
|
|
{
|
|
INF_DIVA20,
|
|
"Dialogic Diva 2.0",
|
|
"diva20",
|
|
AM_IND_IO, AM_NONE, 2, 0,
|
|
&diva_irq
|
|
},
|
|
{
|
|
INF_DIVA20U,
|
|
"Dialogic Diva 2.0U",
|
|
"diva20U",
|
|
AM_IND_IO, AM_NONE, 2, 0,
|
|
&diva_irq
|
|
},
|
|
{
|
|
INF_DIVA201,
|
|
"Dialogic Diva 2.01",
|
|
"diva201",
|
|
AM_MEMIO, AM_MEMIO, 0, 1,
|
|
&diva20x_irq
|
|
},
|
|
{
|
|
INF_DIVA202,
|
|
"Dialogic Diva 2.02",
|
|
"diva202",
|
|
AM_MEMIO, AM_MEMIO, 0, 1,
|
|
&diva20x_irq
|
|
},
|
|
{
|
|
INF_SPEEDWIN,
|
|
"Sedlbauer SpeedWin PCI",
|
|
"speedwin",
|
|
AM_IND_IO, AM_NONE, 0, 0,
|
|
&tiger_irq
|
|
},
|
|
{
|
|
INF_SAPHIR3,
|
|
"HST Saphir 3",
|
|
"saphir",
|
|
AM_IND_IO, AM_NONE, 0, 0,
|
|
&tiger_irq
|
|
},
|
|
{
|
|
INF_QS1000,
|
|
"Develo Microlink PCI",
|
|
"qs1000",
|
|
AM_IO, AM_IND_IO, 1, 3,
|
|
&elsa_irq
|
|
},
|
|
{
|
|
INF_QS3000,
|
|
"Develo QuickStep 3000",
|
|
"qs3000",
|
|
AM_IO, AM_IND_IO, 1, 3,
|
|
&elsa_irq
|
|
},
|
|
{
|
|
INF_NICCY,
|
|
"Sagem NICCY",
|
|
"niccy",
|
|
AM_IO, AM_IND_IO, 0, 1,
|
|
&niccy_irq
|
|
},
|
|
{
|
|
INF_SCT_1,
|
|
"SciTel Quadro",
|
|
"p1_scitel",
|
|
AM_IO, AM_IND_IO, 1, 5,
|
|
&ipac_irq
|
|
},
|
|
{
|
|
INF_SCT_2,
|
|
"SciTel Quadro",
|
|
"p2_scitel",
|
|
AM_NONE, AM_IND_IO, 0, 4,
|
|
&ipac_irq
|
|
},
|
|
{
|
|
INF_SCT_3,
|
|
"SciTel Quadro",
|
|
"p3_scitel",
|
|
AM_NONE, AM_IND_IO, 0, 3,
|
|
&ipac_irq
|
|
},
|
|
{
|
|
INF_SCT_4,
|
|
"SciTel Quadro",
|
|
"p4_scitel",
|
|
AM_NONE, AM_IND_IO, 0, 2,
|
|
&ipac_irq
|
|
},
|
|
{
|
|
INF_GAZEL_R685,
|
|
"Gazel R685",
|
|
"gazel685",
|
|
AM_IO, AM_IO, 1, 2,
|
|
&gazel_irq
|
|
},
|
|
{
|
|
INF_GAZEL_R753,
|
|
"Gazel R753",
|
|
"gazel753",
|
|
AM_IO, AM_IND_IO, 1, 2,
|
|
&ipac_irq
|
|
},
|
|
{
|
|
INF_NONE,
|
|
}
|
|
};
|
|
|
|
static const struct inf_cinfo *
|
|
get_card_info(enum inf_types typ)
|
|
{
|
|
const struct inf_cinfo *ci = inf_card_info;
|
|
|
|
while (ci->typ != INF_NONE) {
|
|
if (ci->typ == typ)
|
|
return ci;
|
|
ci++;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
static int
|
|
inf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
int err = -ENOMEM;
|
|
struct inf_hw *card;
|
|
|
|
card = kzalloc(sizeof(struct inf_hw), GFP_KERNEL);
|
|
if (!card) {
|
|
pr_info("No memory for Infineon ISDN card\n");
|
|
return err;
|
|
}
|
|
card->pdev = pdev;
|
|
err = pci_enable_device(pdev);
|
|
if (err) {
|
|
kfree(card);
|
|
return err;
|
|
}
|
|
card->ci = get_card_info(ent->driver_data);
|
|
if (!card->ci) {
|
|
pr_info("mISDN: do not have information about adapter at %s\n",
|
|
pci_name(pdev));
|
|
kfree(card);
|
|
pci_disable_device(pdev);
|
|
return -EINVAL;
|
|
} else
|
|
pr_notice("mISDN: found adapter %s at %s\n",
|
|
card->ci->full, pci_name(pdev));
|
|
|
|
card->irq = pdev->irq;
|
|
pci_set_drvdata(pdev, card);
|
|
err = setup_instance(card);
|
|
if (err) {
|
|
pci_disable_device(pdev);
|
|
kfree(card);
|
|
pci_set_drvdata(pdev, NULL);
|
|
} else if (ent->driver_data == INF_SCT_1) {
|
|
int i;
|
|
struct inf_hw *sc;
|
|
|
|
for (i = 1; i < 4; i++) {
|
|
sc = kzalloc(sizeof(struct inf_hw), GFP_KERNEL);
|
|
if (!sc) {
|
|
release_card(card);
|
|
pci_disable_device(pdev);
|
|
return -ENOMEM;
|
|
}
|
|
sc->irq = card->irq;
|
|
sc->pdev = card->pdev;
|
|
sc->ci = card->ci + i;
|
|
err = setup_instance(sc);
|
|
if (err) {
|
|
pci_disable_device(pdev);
|
|
kfree(sc);
|
|
release_card(card);
|
|
break;
|
|
} else
|
|
card->sc[i - 1] = sc;
|
|
}
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static void
|
|
inf_remove(struct pci_dev *pdev)
|
|
{
|
|
struct inf_hw *card = pci_get_drvdata(pdev);
|
|
|
|
if (card)
|
|
release_card(card);
|
|
else
|
|
pr_debug("%s: drvdata already removed\n", __func__);
|
|
}
|
|
|
|
static struct pci_driver infineon_driver = {
|
|
.name = "ISDN Infineon pci",
|
|
.probe = inf_probe,
|
|
.remove = inf_remove,
|
|
.id_table = infineon_ids,
|
|
};
|
|
|
|
static int __init
|
|
infineon_init(void)
|
|
{
|
|
int err;
|
|
|
|
pr_notice("Infineon ISDN Driver Rev. %s\n", INFINEON_REV);
|
|
err = pci_register_driver(&infineon_driver);
|
|
return err;
|
|
}
|
|
|
|
static void __exit
|
|
infineon_cleanup(void)
|
|
{
|
|
pci_unregister_driver(&infineon_driver);
|
|
}
|
|
|
|
module_init(infineon_init);
|
|
module_exit(infineon_cleanup);
|