499 lines
14 KiB
C
499 lines
14 KiB
C
#include <media/drv-intf/saa7146_vv.h>
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static int vbi_pixel_to_capture = 720 * 2;
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static int vbi_workaround(struct saa7146_dev *dev)
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{
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struct saa7146_vv *vv = dev->vv_data;
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u32 *cpu;
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dma_addr_t dma_addr;
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int count = 0;
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int i;
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DECLARE_WAITQUEUE(wait, current);
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DEB_VBI("dev:%p\n", dev);
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/* once again, a bug in the saa7146: the brs acquisition
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is buggy and especially the BXO-counter does not work
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as specified. there is this workaround, but please
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don't let me explain it. ;-) */
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cpu = pci_alloc_consistent(dev->pci, 4096, &dma_addr);
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if (NULL == cpu)
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return -ENOMEM;
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/* setup some basic programming, just for the workaround */
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saa7146_write(dev, BASE_EVEN3, dma_addr);
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saa7146_write(dev, BASE_ODD3, dma_addr+vbi_pixel_to_capture);
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saa7146_write(dev, PROT_ADDR3, dma_addr+4096);
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saa7146_write(dev, PITCH3, vbi_pixel_to_capture);
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saa7146_write(dev, BASE_PAGE3, 0x0);
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saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0));
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saa7146_write(dev, MC2, MASK_04|MASK_20);
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/* load brs-control register */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
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/* BXO = 1h, BRS to outbound */
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WRITE_RPS1(0xc000008c);
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/* wait for vbi_a or vbi_b*/
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if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
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DEB_D("...using port b\n");
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WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_E_FID_B);
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WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_O_FID_B);
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/*
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WRITE_RPS1(CMD_PAUSE | MASK_09);
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*/
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} else {
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DEB_D("...using port a\n");
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WRITE_RPS1(CMD_PAUSE | MASK_10);
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}
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/* upload brs */
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WRITE_RPS1(CMD_UPLOAD | MASK_08);
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/* load brs-control register */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
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/* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
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WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
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/* wait for brs_done */
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WRITE_RPS1(CMD_PAUSE | MASK_08);
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/* upload brs */
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WRITE_RPS1(CMD_UPLOAD | MASK_08);
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/* load video-dma3 NumLines3 and NumBytes3 */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
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/* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
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WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
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/* load brs-control register */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
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/* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
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WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
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/* wait for brs_done */
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WRITE_RPS1(CMD_PAUSE | MASK_08);
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/* upload brs and video-dma3*/
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WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
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/* load mc2 register: enable dma3 */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
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WRITE_RPS1(MASK_20 | MASK_04);
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/* generate interrupt */
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WRITE_RPS1(CMD_INTERRUPT);
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/* stop rps1 */
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WRITE_RPS1(CMD_STOP);
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/* we have to do the workaround twice to be sure that
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everything is ok */
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for(i = 0; i < 2; i++) {
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/* indicate to the irq handler that we do the workaround */
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saa7146_write(dev, MC2, MASK_31|MASK_15);
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saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0));
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saa7146_write(dev, MC2, MASK_04|MASK_20);
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/* enable rps1 irqs */
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SAA7146_IER_ENABLE(dev,MASK_28);
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/* prepare to wait to be woken up by the irq-handler */
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add_wait_queue(&vv->vbi_wq, &wait);
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set_current_state(TASK_INTERRUPTIBLE);
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/* start rps1 to enable workaround */
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saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
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saa7146_write(dev, MC1, (MASK_13 | MASK_29));
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schedule();
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DEB_VBI("brs bug workaround %d/1\n", i);
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remove_wait_queue(&vv->vbi_wq, &wait);
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__set_current_state(TASK_RUNNING);
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/* disable rps1 irqs */
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SAA7146_IER_DISABLE(dev,MASK_28);
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/* stop video-dma3 */
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saa7146_write(dev, MC1, MASK_20);
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if(signal_pending(current)) {
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DEB_VBI("aborted (rps:0x%08x)\n",
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saa7146_read(dev, RPS_ADDR1));
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/* stop rps1 for sure */
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saa7146_write(dev, MC1, MASK_29);
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pci_free_consistent(dev->pci, 4096, cpu, dma_addr);
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return -EINTR;
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}
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}
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pci_free_consistent(dev->pci, 4096, cpu, dma_addr);
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return 0;
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}
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static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
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{
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struct saa7146_vv *vv = dev->vv_data;
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struct saa7146_video_dma vdma3;
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int count = 0;
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unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
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unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
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/*
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vdma3.base_even = 0xc8000000+2560*70;
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vdma3.base_odd = 0xc8000000;
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vdma3.prot_addr = 0xc8000000+2560*164;
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vdma3.pitch = 2560;
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vdma3.base_page = 0;
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vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above!
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*/
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vdma3.base_even = buf->pt[2].offset;
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vdma3.base_odd = buf->pt[2].offset + 16 * vbi_pixel_to_capture;
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vdma3.prot_addr = buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture;
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vdma3.pitch = vbi_pixel_to_capture;
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vdma3.base_page = buf->pt[2].dma | ME1;
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vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture;
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saa7146_write_out_dma(dev, 3, &vdma3);
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/* write beginning of rps-program */
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count = 0;
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/* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */
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/* we don't wait here for the first field anymore. this is different from the video
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capture and might cause that the first buffer is only half filled (with only
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one field). but since this is some sort of streaming data, this is not that negative.
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but by doing this, we can use the whole engine from videobuf-dma-sg.c... */
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/*
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WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait);
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WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait);
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*/
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/* set bit 1 */
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WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
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WRITE_RPS1(MASK_28 | MASK_12);
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/* turn on video-dma3 */
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WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
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WRITE_RPS1(MASK_04 | MASK_20); /* => mask */
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WRITE_RPS1(MASK_04 | MASK_20); /* => values */
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/* wait for o_fid_a/b / e_fid_a/b toggle */
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WRITE_RPS1(CMD_PAUSE | o_wait);
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WRITE_RPS1(CMD_PAUSE | e_wait);
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/* generate interrupt */
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WRITE_RPS1(CMD_INTERRUPT);
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/* stop */
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WRITE_RPS1(CMD_STOP);
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/* enable rps1 irqs */
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SAA7146_IER_ENABLE(dev, MASK_28);
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/* write the address of the rps-program */
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saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
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/* turn on rps */
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saa7146_write(dev, MC1, (MASK_13 | MASK_29));
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}
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static int buffer_activate(struct saa7146_dev *dev,
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struct saa7146_buf *buf,
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struct saa7146_buf *next)
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{
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struct saa7146_vv *vv = dev->vv_data;
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buf->vb.state = VIDEOBUF_ACTIVE;
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DEB_VBI("dev:%p, buf:%p, next:%p\n", dev, buf, next);
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saa7146_set_vbi_capture(dev,buf,next);
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mod_timer(&vv->vbi_dmaq.timeout, jiffies+BUFFER_TIMEOUT);
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return 0;
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}
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static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,enum v4l2_field field)
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{
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struct file *file = q->priv_data;
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struct saa7146_fh *fh = file->private_data;
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struct saa7146_dev *dev = fh->dev;
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struct saa7146_buf *buf = (struct saa7146_buf *)vb;
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int err = 0;
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int lines, llength, size;
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lines = 16 * 2 ; /* 2 fields */
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llength = vbi_pixel_to_capture;
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size = lines * llength;
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DEB_VBI("vb:%p\n", vb);
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if (0 != buf->vb.baddr && buf->vb.bsize < size) {
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DEB_VBI("size mismatch\n");
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return -EINVAL;
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}
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if (buf->vb.size != size)
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saa7146_dma_free(dev,q,buf);
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if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
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struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb);
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buf->vb.width = llength;
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buf->vb.height = lines;
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buf->vb.size = size;
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buf->vb.field = field; // FIXME: check this
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saa7146_pgtable_free(dev->pci, &buf->pt[2]);
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saa7146_pgtable_alloc(dev->pci, &buf->pt[2]);
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err = videobuf_iolock(q,&buf->vb, NULL);
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if (err)
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goto oops;
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err = saa7146_pgtable_build_single(dev->pci, &buf->pt[2],
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dma->sglist, dma->sglen);
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if (0 != err)
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return err;
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}
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buf->vb.state = VIDEOBUF_PREPARED;
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buf->activate = buffer_activate;
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return 0;
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oops:
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DEB_VBI("error out\n");
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saa7146_dma_free(dev,q,buf);
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return err;
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}
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static int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size)
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{
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int llength,lines;
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lines = 16 * 2 ; /* 2 fields */
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llength = vbi_pixel_to_capture;
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*size = lines * llength;
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*count = 2;
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DEB_VBI("count:%d, size:%d\n", *count, *size);
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return 0;
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}
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static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
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{
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struct file *file = q->priv_data;
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struct saa7146_fh *fh = file->private_data;
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struct saa7146_dev *dev = fh->dev;
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struct saa7146_vv *vv = dev->vv_data;
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struct saa7146_buf *buf = (struct saa7146_buf *)vb;
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DEB_VBI("vb:%p\n", vb);
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saa7146_buffer_queue(dev, &vv->vbi_dmaq, buf);
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}
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static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
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{
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struct file *file = q->priv_data;
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struct saa7146_fh *fh = file->private_data;
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struct saa7146_dev *dev = fh->dev;
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struct saa7146_buf *buf = (struct saa7146_buf *)vb;
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DEB_VBI("vb:%p\n", vb);
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saa7146_dma_free(dev,q,buf);
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}
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static struct videobuf_queue_ops vbi_qops = {
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.buf_setup = buffer_setup,
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.buf_prepare = buffer_prepare,
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.buf_queue = buffer_queue,
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.buf_release = buffer_release,
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};
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/* ------------------------------------------------------------------ */
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static void vbi_stop(struct saa7146_fh *fh, struct file *file)
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{
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struct saa7146_dev *dev = fh->dev;
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struct saa7146_vv *vv = dev->vv_data;
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unsigned long flags;
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DEB_VBI("dev:%p, fh:%p\n", dev, fh);
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spin_lock_irqsave(&dev->slock,flags);
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/* disable rps1 */
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saa7146_write(dev, MC1, MASK_29);
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/* disable rps1 irqs */
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SAA7146_IER_DISABLE(dev, MASK_28);
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/* shut down dma 3 transfers */
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saa7146_write(dev, MC1, MASK_20);
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if (vv->vbi_dmaq.curr)
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saa7146_buffer_finish(dev, &vv->vbi_dmaq, VIDEOBUF_DONE);
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videobuf_queue_cancel(&fh->vbi_q);
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vv->vbi_streaming = NULL;
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del_timer(&vv->vbi_dmaq.timeout);
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del_timer(&vv->vbi_read_timeout);
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spin_unlock_irqrestore(&dev->slock, flags);
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}
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static void vbi_read_timeout(unsigned long data)
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{
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struct file *file = (struct file*)data;
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struct saa7146_fh *fh = file->private_data;
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struct saa7146_dev *dev = fh->dev;
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DEB_VBI("dev:%p, fh:%p\n", dev, fh);
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vbi_stop(fh, file);
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}
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static void vbi_init(struct saa7146_dev *dev, struct saa7146_vv *vv)
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{
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DEB_VBI("dev:%p\n", dev);
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INIT_LIST_HEAD(&vv->vbi_dmaq.queue);
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init_timer(&vv->vbi_dmaq.timeout);
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vv->vbi_dmaq.timeout.function = saa7146_buffer_timeout;
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vv->vbi_dmaq.timeout.data = (unsigned long)(&vv->vbi_dmaq);
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vv->vbi_dmaq.dev = dev;
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init_waitqueue_head(&vv->vbi_wq);
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}
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static int vbi_open(struct saa7146_dev *dev, struct file *file)
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{
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struct saa7146_fh *fh = file->private_data;
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struct saa7146_vv *vv = fh->dev->vv_data;
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u32 arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
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int ret = 0;
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DEB_VBI("dev:%p, fh:%p\n", dev, fh);
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ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS);
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if (0 == ret) {
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DEB_S("cannot get vbi RESOURCE_DMA3_BRS resource\n");
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return -EBUSY;
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}
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/* adjust arbitrition control for video dma 3 */
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arbtr_ctrl &= ~0x1f0000;
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arbtr_ctrl |= 0x1d0000;
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saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
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saa7146_write(dev, MC2, (MASK_04|MASK_20));
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videobuf_queue_sg_init(&fh->vbi_q, &vbi_qops,
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&dev->pci->dev, &dev->slock,
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V4L2_BUF_TYPE_VBI_CAPTURE,
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V4L2_FIELD_SEQ_TB, // FIXME: does this really work?
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sizeof(struct saa7146_buf),
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file, &dev->v4l2_lock);
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vv->vbi_read_timeout.function = vbi_read_timeout;
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vv->vbi_read_timeout.data = (unsigned long)file;
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/* initialize the brs */
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if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
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saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
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} else {
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saa7146_write(dev, BRS_CTRL, 0x00000001);
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if (0 != (ret = vbi_workaround(dev))) {
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DEB_VBI("vbi workaround failed!\n");
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/* return ret;*/
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}
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}
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/* upload brs register */
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saa7146_write(dev, MC2, (MASK_08|MASK_24));
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return 0;
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}
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static void vbi_close(struct saa7146_dev *dev, struct file *file)
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{
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struct saa7146_fh *fh = file->private_data;
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struct saa7146_vv *vv = dev->vv_data;
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DEB_VBI("dev:%p, fh:%p\n", dev, fh);
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if( fh == vv->vbi_streaming ) {
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vbi_stop(fh, file);
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}
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saa7146_res_free(fh, RESOURCE_DMA3_BRS);
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}
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static void vbi_irq_done(struct saa7146_dev *dev, unsigned long status)
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{
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struct saa7146_vv *vv = dev->vv_data;
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spin_lock(&dev->slock);
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if (vv->vbi_dmaq.curr) {
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DEB_VBI("dev:%p, curr:%p\n", dev, vv->vbi_dmaq.curr);
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/* this must be += 2, one count for each field */
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vv->vbi_fieldcount+=2;
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vv->vbi_dmaq.curr->vb.field_count = vv->vbi_fieldcount;
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saa7146_buffer_finish(dev, &vv->vbi_dmaq, VIDEOBUF_DONE);
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} else {
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DEB_VBI("dev:%p\n", dev);
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}
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saa7146_buffer_next(dev, &vv->vbi_dmaq, 1);
|
|
|
|
spin_unlock(&dev->slock);
|
|
}
|
|
|
|
static ssize_t vbi_read(struct file *file, char __user *data, size_t count, loff_t *ppos)
|
|
{
|
|
struct saa7146_fh *fh = file->private_data;
|
|
struct saa7146_dev *dev = fh->dev;
|
|
struct saa7146_vv *vv = dev->vv_data;
|
|
ssize_t ret = 0;
|
|
|
|
DEB_VBI("dev:%p, fh:%p\n", dev, fh);
|
|
|
|
if( NULL == vv->vbi_streaming ) {
|
|
// fixme: check if dma3 is available
|
|
// fixme: activate vbi engine here if necessary. (really?)
|
|
vv->vbi_streaming = fh;
|
|
}
|
|
|
|
if( fh != vv->vbi_streaming ) {
|
|
DEB_VBI("open %p is already using vbi capture\n",
|
|
vv->vbi_streaming);
|
|
return -EBUSY;
|
|
}
|
|
|
|
mod_timer(&vv->vbi_read_timeout, jiffies+BUFFER_TIMEOUT);
|
|
ret = videobuf_read_stream(&fh->vbi_q, data, count, ppos, 1,
|
|
file->f_flags & O_NONBLOCK);
|
|
/*
|
|
printk("BASE_ODD3: 0x%08x\n", saa7146_read(dev, BASE_ODD3));
|
|
printk("BASE_EVEN3: 0x%08x\n", saa7146_read(dev, BASE_EVEN3));
|
|
printk("PROT_ADDR3: 0x%08x\n", saa7146_read(dev, PROT_ADDR3));
|
|
printk("PITCH3: 0x%08x\n", saa7146_read(dev, PITCH3));
|
|
printk("BASE_PAGE3: 0x%08x\n", saa7146_read(dev, BASE_PAGE3));
|
|
printk("NUM_LINE_BYTE3: 0x%08x\n", saa7146_read(dev, NUM_LINE_BYTE3));
|
|
printk("BRS_CTRL: 0x%08x\n", saa7146_read(dev, BRS_CTRL));
|
|
*/
|
|
return ret;
|
|
}
|
|
|
|
struct saa7146_use_ops saa7146_vbi_uops = {
|
|
.init = vbi_init,
|
|
.open = vbi_open,
|
|
.release = vbi_close,
|
|
.irq_done = vbi_irq_done,
|
|
.read = vbi_read,
|
|
};
|