871 lines
18 KiB
C
871 lines
18 KiB
C
/*
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* HDIC HD29L2 DMB-TH demodulator driver
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*
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* Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
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*
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* Author: Antti Palosaari <crope@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "hd29l2_priv.h"
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#define HD29L2_MAX_LEN (3)
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/* write multiple registers */
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static int hd29l2_wr_regs(struct hd29l2_priv *priv, u8 reg, u8 *val, int len)
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{
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int ret;
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u8 buf[2 + HD29L2_MAX_LEN];
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struct i2c_msg msg[1] = {
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{
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.addr = priv->cfg.i2c_addr,
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.flags = 0,
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.len = 2 + len,
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.buf = buf,
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}
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};
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if (len > HD29L2_MAX_LEN)
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return -EINVAL;
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buf[0] = 0x00;
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buf[1] = reg;
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memcpy(&buf[2], val, len);
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ret = i2c_transfer(priv->i2c, msg, 1);
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if (ret == 1) {
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ret = 0;
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} else {
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dev_warn(&priv->i2c->dev,
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"%s: i2c wr failed=%d reg=%02x len=%d\n",
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KBUILD_MODNAME, ret, reg, len);
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ret = -EREMOTEIO;
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}
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return ret;
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}
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/* read multiple registers */
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static int hd29l2_rd_regs(struct hd29l2_priv *priv, u8 reg, u8 *val, int len)
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{
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int ret;
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u8 buf[2] = { 0x00, reg };
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struct i2c_msg msg[2] = {
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{
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.addr = priv->cfg.i2c_addr,
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.flags = 0,
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.len = 2,
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.buf = buf,
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}, {
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.addr = priv->cfg.i2c_addr,
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.flags = I2C_M_RD,
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.len = len,
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.buf = val,
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}
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};
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ret = i2c_transfer(priv->i2c, msg, 2);
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if (ret == 2) {
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ret = 0;
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} else {
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dev_warn(&priv->i2c->dev,
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"%s: i2c rd failed=%d reg=%02x len=%d\n",
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KBUILD_MODNAME, ret, reg, len);
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ret = -EREMOTEIO;
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}
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return ret;
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}
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/* write single register */
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static int hd29l2_wr_reg(struct hd29l2_priv *priv, u8 reg, u8 val)
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{
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return hd29l2_wr_regs(priv, reg, &val, 1);
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}
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/* read single register */
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static int hd29l2_rd_reg(struct hd29l2_priv *priv, u8 reg, u8 *val)
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{
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return hd29l2_rd_regs(priv, reg, val, 1);
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}
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/* write single register with mask */
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static int hd29l2_wr_reg_mask(struct hd29l2_priv *priv, u8 reg, u8 val, u8 mask)
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{
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int ret;
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u8 tmp;
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/* no need for read if whole reg is written */
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if (mask != 0xff) {
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ret = hd29l2_rd_regs(priv, reg, &tmp, 1);
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if (ret)
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return ret;
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val &= mask;
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tmp &= ~mask;
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val |= tmp;
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}
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return hd29l2_wr_regs(priv, reg, &val, 1);
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}
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/* read single register with mask */
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static int hd29l2_rd_reg_mask(struct hd29l2_priv *priv, u8 reg, u8 *val, u8 mask)
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{
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int ret, i;
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u8 tmp;
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ret = hd29l2_rd_regs(priv, reg, &tmp, 1);
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if (ret)
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return ret;
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tmp &= mask;
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/* find position of the first bit */
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for (i = 0; i < 8; i++) {
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if ((mask >> i) & 0x01)
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break;
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}
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*val = tmp >> i;
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return 0;
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}
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static int hd29l2_soft_reset(struct hd29l2_priv *priv)
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{
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int ret;
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u8 tmp;
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ret = hd29l2_rd_reg(priv, 0x26, &tmp);
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if (ret)
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goto err;
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ret = hd29l2_wr_reg(priv, 0x26, 0x0d);
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if (ret)
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goto err;
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usleep_range(10000, 20000);
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ret = hd29l2_wr_reg(priv, 0x26, tmp);
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if (ret)
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goto err;
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return 0;
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err:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int hd29l2_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
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{
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int ret, i;
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struct hd29l2_priv *priv = fe->demodulator_priv;
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u8 tmp;
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dev_dbg(&priv->i2c->dev, "%s: enable=%d\n", __func__, enable);
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/* set tuner address for demod */
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if (!priv->tuner_i2c_addr_programmed && enable) {
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/* no need to set tuner address every time, once is enough */
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ret = hd29l2_wr_reg(priv, 0x9d, priv->cfg.tuner_i2c_addr << 1);
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if (ret)
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goto err;
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priv->tuner_i2c_addr_programmed = true;
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}
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/* open / close gate */
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ret = hd29l2_wr_reg(priv, 0x9f, enable);
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if (ret)
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goto err;
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/* wait demod ready */
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for (i = 10; i; i--) {
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ret = hd29l2_rd_reg(priv, 0x9e, &tmp);
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if (ret)
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goto err;
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if (tmp == enable)
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break;
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usleep_range(5000, 10000);
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}
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dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
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return ret;
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err:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int hd29l2_read_status(struct dvb_frontend *fe, enum fe_status *status)
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{
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int ret;
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struct hd29l2_priv *priv = fe->demodulator_priv;
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u8 buf[2];
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*status = 0;
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ret = hd29l2_rd_reg(priv, 0x05, &buf[0]);
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if (ret)
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goto err;
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if (buf[0] & 0x01) {
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/* full lock */
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*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
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FE_HAS_SYNC | FE_HAS_LOCK;
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} else {
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ret = hd29l2_rd_reg(priv, 0x0d, &buf[1]);
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if (ret)
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goto err;
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if ((buf[1] & 0xfe) == 0x78)
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/* partial lock */
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*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC;
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}
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priv->fe_status = *status;
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return 0;
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err:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int hd29l2_read_snr(struct dvb_frontend *fe, u16 *snr)
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{
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int ret;
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struct hd29l2_priv *priv = fe->demodulator_priv;
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u8 buf[2];
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u16 tmp;
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if (!(priv->fe_status & FE_HAS_LOCK)) {
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*snr = 0;
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ret = 0;
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goto err;
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}
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ret = hd29l2_rd_regs(priv, 0x0b, buf, 2);
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if (ret)
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goto err;
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tmp = (buf[0] << 8) | buf[1];
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/* report SNR in dB * 10 */
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#define LOG10_20736_24 72422627 /* log10(20736) << 24 */
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if (tmp)
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*snr = (LOG10_20736_24 - intlog10(tmp)) / ((1 << 24) / 100);
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else
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*snr = 0;
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return 0;
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err:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int hd29l2_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
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{
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int ret;
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struct hd29l2_priv *priv = fe->demodulator_priv;
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u8 buf[2];
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u16 tmp;
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*strength = 0;
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ret = hd29l2_rd_regs(priv, 0xd5, buf, 2);
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if (ret)
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goto err;
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tmp = buf[0] << 8 | buf[1];
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tmp = ~tmp & 0x0fff;
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/* scale value to 0x0000-0xffff from 0x0000-0x0fff */
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*strength = tmp * 0xffff / 0x0fff;
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return 0;
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err:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int hd29l2_read_ber(struct dvb_frontend *fe, u32 *ber)
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{
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int ret;
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struct hd29l2_priv *priv = fe->demodulator_priv;
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u8 buf[2];
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if (!(priv->fe_status & FE_HAS_SYNC)) {
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*ber = 0;
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ret = 0;
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goto err;
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}
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ret = hd29l2_rd_regs(priv, 0xd9, buf, 2);
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if (ret) {
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*ber = 0;
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goto err;
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}
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/* LDPC BER */
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*ber = ((buf[0] & 0x0f) << 8) | buf[1];
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return 0;
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err:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int hd29l2_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
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{
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/* no way to read? */
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*ucblocks = 0;
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return 0;
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}
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static enum dvbfe_search hd29l2_search(struct dvb_frontend *fe)
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{
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int ret, i;
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struct hd29l2_priv *priv = fe->demodulator_priv;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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u8 tmp, buf[3];
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u8 modulation, carrier, guard_interval, interleave, code_rate;
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u64 num64;
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u32 if_freq, if_ctl;
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bool auto_mode;
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dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d frequency=%d " \
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"bandwidth_hz=%d modulation=%d inversion=%d " \
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"fec_inner=%d guard_interval=%d\n", __func__,
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c->delivery_system, c->frequency, c->bandwidth_hz,
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c->modulation, c->inversion, c->fec_inner,
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c->guard_interval);
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/* as for now we detect always params automatically */
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auto_mode = true;
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/* program tuner */
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if (fe->ops.tuner_ops.set_params)
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fe->ops.tuner_ops.set_params(fe);
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/* get and program IF */
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if (fe->ops.tuner_ops.get_if_frequency)
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fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
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else
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if_freq = 0;
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if (if_freq) {
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/* normal IF */
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/* calc IF control value */
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num64 = if_freq;
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num64 *= 0x800000;
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num64 = div_u64(num64, HD29L2_XTAL);
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num64 -= 0x800000;
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if_ctl = num64;
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tmp = 0xfc; /* tuner type normal */
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} else {
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/* zero IF */
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if_ctl = 0;
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tmp = 0xfe; /* tuner type Zero-IF */
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}
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buf[0] = ((if_ctl >> 0) & 0xff);
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buf[1] = ((if_ctl >> 8) & 0xff);
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buf[2] = ((if_ctl >> 16) & 0xff);
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/* program IF control */
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ret = hd29l2_wr_regs(priv, 0x14, buf, 3);
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if (ret)
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goto err;
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/* program tuner type */
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ret = hd29l2_wr_reg(priv, 0xab, tmp);
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if (ret)
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goto err;
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dev_dbg(&priv->i2c->dev, "%s: if_freq=%d if_ctl=%x\n",
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__func__, if_freq, if_ctl);
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if (auto_mode) {
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/*
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* use auto mode
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*/
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/* disable quick mode */
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ret = hd29l2_wr_reg_mask(priv, 0xac, 0 << 7, 0x80);
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if (ret)
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goto err;
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ret = hd29l2_wr_reg_mask(priv, 0x82, 1 << 1, 0x02);
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if (ret)
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goto err;
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/* enable auto mode */
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ret = hd29l2_wr_reg_mask(priv, 0x7d, 1 << 6, 0x40);
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if (ret)
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goto err;
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ret = hd29l2_wr_reg_mask(priv, 0x81, 1 << 3, 0x08);
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if (ret)
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goto err;
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/* soft reset */
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ret = hd29l2_soft_reset(priv);
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if (ret)
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goto err;
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/* detect modulation */
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for (i = 30; i; i--) {
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msleep(100);
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ret = hd29l2_rd_reg(priv, 0x0d, &tmp);
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if (ret)
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goto err;
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if ((((tmp & 0xf0) >= 0x10) &&
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((tmp & 0x0f) == 0x08)) || (tmp >= 0x2c))
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break;
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}
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dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
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if (i == 0)
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/* detection failed */
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return DVBFE_ALGO_SEARCH_FAILED;
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/* read modulation */
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ret = hd29l2_rd_reg_mask(priv, 0x7d, &modulation, 0x07);
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if (ret)
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goto err;
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} else {
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/*
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* use manual mode
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*/
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modulation = HD29L2_QAM64;
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carrier = HD29L2_CARRIER_MULTI;
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guard_interval = HD29L2_PN945;
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interleave = HD29L2_INTERLEAVER_420;
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code_rate = HD29L2_CODE_RATE_08;
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tmp = (code_rate << 3) | modulation;
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ret = hd29l2_wr_reg_mask(priv, 0x7d, tmp, 0x5f);
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if (ret)
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goto err;
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tmp = (carrier << 2) | guard_interval;
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ret = hd29l2_wr_reg_mask(priv, 0x81, tmp, 0x0f);
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if (ret)
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goto err;
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tmp = interleave;
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ret = hd29l2_wr_reg_mask(priv, 0x82, tmp, 0x03);
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if (ret)
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goto err;
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}
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/* ensure modulation validy */
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/* 0=QAM4_NR, 1=QAM4, 2=QAM16, 3=QAM32, 4=QAM64 */
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if (modulation > (ARRAY_SIZE(reg_mod_vals_tab[0].val) - 1)) {
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dev_dbg(&priv->i2c->dev, "%s: modulation=%d not valid\n",
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__func__, modulation);
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goto err;
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}
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/* program registers according to modulation */
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for (i = 0; i < ARRAY_SIZE(reg_mod_vals_tab); i++) {
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ret = hd29l2_wr_reg(priv, reg_mod_vals_tab[i].reg,
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reg_mod_vals_tab[i].val[modulation]);
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if (ret)
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goto err;
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}
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/* read guard interval */
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ret = hd29l2_rd_reg_mask(priv, 0x81, &guard_interval, 0x03);
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if (ret)
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goto err;
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/* read carrier mode */
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ret = hd29l2_rd_reg_mask(priv, 0x81, &carrier, 0x04);
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if (ret)
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goto err;
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dev_dbg(&priv->i2c->dev,
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"%s: modulation=%d guard_interval=%d carrier=%d\n",
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__func__, modulation, guard_interval, carrier);
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if ((carrier == HD29L2_CARRIER_MULTI) && (modulation == HD29L2_QAM64) &&
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(guard_interval == HD29L2_PN945)) {
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dev_dbg(&priv->i2c->dev, "%s: C=3780 && QAM64 && PN945\n",
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__func__);
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ret = hd29l2_wr_reg(priv, 0x42, 0x33);
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if (ret)
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goto err;
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ret = hd29l2_wr_reg(priv, 0xdd, 0x01);
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if (ret)
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goto err;
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}
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usleep_range(10000, 20000);
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/* soft reset */
|
|
ret = hd29l2_soft_reset(priv);
|
|
if (ret)
|
|
goto err;
|
|
|
|
/* wait demod lock */
|
|
for (i = 30; i; i--) {
|
|
msleep(100);
|
|
|
|
/* read lock bit */
|
|
ret = hd29l2_rd_reg_mask(priv, 0x05, &tmp, 0x01);
|
|
if (ret)
|
|
goto err;
|
|
|
|
if (tmp)
|
|
break;
|
|
}
|
|
|
|
dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
|
|
|
|
if (i == 0)
|
|
return DVBFE_ALGO_SEARCH_AGAIN;
|
|
|
|
return DVBFE_ALGO_SEARCH_SUCCESS;
|
|
err:
|
|
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
|
|
return DVBFE_ALGO_SEARCH_ERROR;
|
|
}
|
|
|
|
static int hd29l2_get_frontend_algo(struct dvb_frontend *fe)
|
|
{
|
|
return DVBFE_ALGO_CUSTOM;
|
|
}
|
|
|
|
static int hd29l2_get_frontend(struct dvb_frontend *fe,
|
|
struct dtv_frontend_properties *c)
|
|
{
|
|
int ret;
|
|
struct hd29l2_priv *priv = fe->demodulator_priv;
|
|
u8 buf[3];
|
|
u32 if_ctl;
|
|
char *str_constellation, *str_code_rate, *str_constellation_code_rate,
|
|
*str_guard_interval, *str_carrier, *str_guard_interval_carrier,
|
|
*str_interleave, *str_interleave_;
|
|
|
|
ret = hd29l2_rd_reg(priv, 0x7d, &buf[0]);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = hd29l2_rd_regs(priv, 0x81, &buf[1], 2);
|
|
if (ret)
|
|
goto err;
|
|
|
|
/* constellation, 0x7d[2:0] */
|
|
switch ((buf[0] >> 0) & 0x07) {
|
|
case 0: /* QAM4NR */
|
|
str_constellation = "QAM4NR";
|
|
c->modulation = QAM_AUTO; /* FIXME */
|
|
break;
|
|
case 1: /* QAM4 */
|
|
str_constellation = "QAM4";
|
|
c->modulation = QPSK; /* FIXME */
|
|
break;
|
|
case 2:
|
|
str_constellation = "QAM16";
|
|
c->modulation = QAM_16;
|
|
break;
|
|
case 3:
|
|
str_constellation = "QAM32";
|
|
c->modulation = QAM_32;
|
|
break;
|
|
case 4:
|
|
str_constellation = "QAM64";
|
|
c->modulation = QAM_64;
|
|
break;
|
|
default:
|
|
str_constellation = "?";
|
|
}
|
|
|
|
/* LDPC code rate, 0x7d[4:3] */
|
|
switch ((buf[0] >> 3) & 0x03) {
|
|
case 0: /* 0.4 */
|
|
str_code_rate = "0.4";
|
|
c->fec_inner = FEC_AUTO; /* FIXME */
|
|
break;
|
|
case 1: /* 0.6 */
|
|
str_code_rate = "0.6";
|
|
c->fec_inner = FEC_3_5;
|
|
break;
|
|
case 2: /* 0.8 */
|
|
str_code_rate = "0.8";
|
|
c->fec_inner = FEC_4_5;
|
|
break;
|
|
default:
|
|
str_code_rate = "?";
|
|
}
|
|
|
|
/* constellation & code rate set, 0x7d[6] */
|
|
switch ((buf[0] >> 6) & 0x01) {
|
|
case 0:
|
|
str_constellation_code_rate = "manual";
|
|
break;
|
|
case 1:
|
|
str_constellation_code_rate = "auto";
|
|
break;
|
|
default:
|
|
str_constellation_code_rate = "?";
|
|
}
|
|
|
|
/* frame header, 0x81[1:0] */
|
|
switch ((buf[1] >> 0) & 0x03) {
|
|
case 0: /* PN945 */
|
|
str_guard_interval = "PN945";
|
|
c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
|
|
break;
|
|
case 1: /* PN595 */
|
|
str_guard_interval = "PN595";
|
|
c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
|
|
break;
|
|
case 2: /* PN420 */
|
|
str_guard_interval = "PN420";
|
|
c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
|
|
break;
|
|
default:
|
|
str_guard_interval = "?";
|
|
}
|
|
|
|
/* carrier, 0x81[2] */
|
|
switch ((buf[1] >> 2) & 0x01) {
|
|
case 0:
|
|
str_carrier = "C=1";
|
|
break;
|
|
case 1:
|
|
str_carrier = "C=3780";
|
|
break;
|
|
default:
|
|
str_carrier = "?";
|
|
}
|
|
|
|
/* frame header & carrier set, 0x81[3] */
|
|
switch ((buf[1] >> 3) & 0x01) {
|
|
case 0:
|
|
str_guard_interval_carrier = "manual";
|
|
break;
|
|
case 1:
|
|
str_guard_interval_carrier = "auto";
|
|
break;
|
|
default:
|
|
str_guard_interval_carrier = "?";
|
|
}
|
|
|
|
/* interleave, 0x82[0] */
|
|
switch ((buf[2] >> 0) & 0x01) {
|
|
case 0:
|
|
str_interleave = "M=720";
|
|
break;
|
|
case 1:
|
|
str_interleave = "M=240";
|
|
break;
|
|
default:
|
|
str_interleave = "?";
|
|
}
|
|
|
|
/* interleave set, 0x82[1] */
|
|
switch ((buf[2] >> 1) & 0x01) {
|
|
case 0:
|
|
str_interleave_ = "manual";
|
|
break;
|
|
case 1:
|
|
str_interleave_ = "auto";
|
|
break;
|
|
default:
|
|
str_interleave_ = "?";
|
|
}
|
|
|
|
/*
|
|
* We can read out current detected NCO and use that value next
|
|
* time instead of calculating new value from targed IF.
|
|
* I think it will not effect receiver sensitivity but gaining lock
|
|
* after tune could be easier...
|
|
*/
|
|
ret = hd29l2_rd_regs(priv, 0xb1, &buf[0], 3);
|
|
if (ret)
|
|
goto err;
|
|
|
|
if_ctl = (buf[0] << 16) | ((buf[1] - 7) << 8) | buf[2];
|
|
|
|
dev_dbg(&priv->i2c->dev, "%s: %s %s %s | %s %s %s | %s %s | NCO=%06x\n",
|
|
__func__, str_constellation, str_code_rate,
|
|
str_constellation_code_rate, str_guard_interval,
|
|
str_carrier, str_guard_interval_carrier, str_interleave,
|
|
str_interleave_, if_ctl);
|
|
return 0;
|
|
err:
|
|
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
static int hd29l2_init(struct dvb_frontend *fe)
|
|
{
|
|
int ret, i;
|
|
struct hd29l2_priv *priv = fe->demodulator_priv;
|
|
u8 tmp;
|
|
static const struct reg_val tab[] = {
|
|
{ 0x3a, 0x06 },
|
|
{ 0x3b, 0x03 },
|
|
{ 0x3c, 0x04 },
|
|
{ 0xaf, 0x06 },
|
|
{ 0xb0, 0x1b },
|
|
{ 0x80, 0x64 },
|
|
{ 0x10, 0x38 },
|
|
};
|
|
|
|
dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
|
|
|
|
/* reset demod */
|
|
/* it is recommended to HW reset chip using RST_N pin */
|
|
if (fe->callback) {
|
|
ret = fe->callback(fe, DVB_FRONTEND_COMPONENT_DEMOD, 0, 0);
|
|
if (ret)
|
|
goto err;
|
|
|
|
/* reprogramming needed because HW reset clears registers */
|
|
priv->tuner_i2c_addr_programmed = false;
|
|
}
|
|
|
|
/* init */
|
|
for (i = 0; i < ARRAY_SIZE(tab); i++) {
|
|
ret = hd29l2_wr_reg(priv, tab[i].reg, tab[i].val);
|
|
if (ret)
|
|
goto err;
|
|
}
|
|
|
|
/* TS params */
|
|
ret = hd29l2_rd_reg(priv, 0x36, &tmp);
|
|
if (ret)
|
|
goto err;
|
|
|
|
tmp &= 0x1b;
|
|
tmp |= priv->cfg.ts_mode;
|
|
ret = hd29l2_wr_reg(priv, 0x36, tmp);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = hd29l2_rd_reg(priv, 0x31, &tmp);
|
|
tmp &= 0xef;
|
|
|
|
if (!(priv->cfg.ts_mode >> 7))
|
|
/* set b4 for serial TS */
|
|
tmp |= 0x10;
|
|
|
|
ret = hd29l2_wr_reg(priv, 0x31, tmp);
|
|
if (ret)
|
|
goto err;
|
|
|
|
return ret;
|
|
err:
|
|
dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
static void hd29l2_release(struct dvb_frontend *fe)
|
|
{
|
|
struct hd29l2_priv *priv = fe->demodulator_priv;
|
|
kfree(priv);
|
|
}
|
|
|
|
static struct dvb_frontend_ops hd29l2_ops;
|
|
|
|
struct dvb_frontend *hd29l2_attach(const struct hd29l2_config *config,
|
|
struct i2c_adapter *i2c)
|
|
{
|
|
int ret;
|
|
struct hd29l2_priv *priv = NULL;
|
|
u8 tmp;
|
|
|
|
/* allocate memory for the internal state */
|
|
priv = kzalloc(sizeof(struct hd29l2_priv), GFP_KERNEL);
|
|
if (priv == NULL)
|
|
goto err;
|
|
|
|
/* setup the state */
|
|
priv->i2c = i2c;
|
|
memcpy(&priv->cfg, config, sizeof(struct hd29l2_config));
|
|
|
|
|
|
/* check if the demod is there */
|
|
ret = hd29l2_rd_reg(priv, 0x00, &tmp);
|
|
if (ret)
|
|
goto err;
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&priv->fe.ops, &hd29l2_ops, sizeof(struct dvb_frontend_ops));
|
|
priv->fe.demodulator_priv = priv;
|
|
|
|
return &priv->fe;
|
|
err:
|
|
kfree(priv);
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL(hd29l2_attach);
|
|
|
|
static struct dvb_frontend_ops hd29l2_ops = {
|
|
.delsys = { SYS_DVBT },
|
|
.info = {
|
|
.name = "HDIC HD29L2 DMB-TH",
|
|
.frequency_min = 474000000,
|
|
.frequency_max = 858000000,
|
|
.frequency_stepsize = 10000,
|
|
.caps = FE_CAN_FEC_AUTO |
|
|
FE_CAN_QPSK |
|
|
FE_CAN_QAM_16 |
|
|
FE_CAN_QAM_32 |
|
|
FE_CAN_QAM_64 |
|
|
FE_CAN_QAM_AUTO |
|
|
FE_CAN_TRANSMISSION_MODE_AUTO |
|
|
FE_CAN_BANDWIDTH_AUTO |
|
|
FE_CAN_GUARD_INTERVAL_AUTO |
|
|
FE_CAN_HIERARCHY_AUTO |
|
|
FE_CAN_RECOVER
|
|
},
|
|
|
|
.release = hd29l2_release,
|
|
|
|
.init = hd29l2_init,
|
|
|
|
.get_frontend_algo = hd29l2_get_frontend_algo,
|
|
.search = hd29l2_search,
|
|
.get_frontend = hd29l2_get_frontend,
|
|
|
|
.read_status = hd29l2_read_status,
|
|
.read_snr = hd29l2_read_snr,
|
|
.read_signal_strength = hd29l2_read_signal_strength,
|
|
.read_ber = hd29l2_read_ber,
|
|
.read_ucblocks = hd29l2_read_ucblocks,
|
|
|
|
.i2c_gate_ctrl = hd29l2_i2c_gate_ctrl,
|
|
};
|
|
|
|
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
|
|
MODULE_DESCRIPTION("HDIC HD29L2 DMB-TH demodulator driver");
|
|
MODULE_LICENSE("GPL");
|